CN109217951B - Transmission delay testing method and device based on FPGA - Google Patents
Transmission delay testing method and device based on FPGA Download PDFInfo
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Abstract
The invention provides a transmission delay test method and a device based on FPGA, which simulate two clock phases which are continuously tightened by two clocks with different periods, determine the alignment time of effective clock edges of the two clocks by an edge synchronous detection unit, determine the time that a fast clock can not acquire a slow clock signal by a signal receiving determination unit, calculate the phase difference of the two clocks according to the number counted by a counter in the time interval from the alignment of the effective clock edges of the two clocks to the time that the fast clock can not acquire the slow clock signal, and determine the transmission delay of a circuit to be tested by combining the calculated phase difference with the period of the slow clock, thereby effectively improving the accuracy of the transmission delay test, leading a user to be capable of reasonably reducing the design margin when the FPGA is applied and fully playing the using performance of an FPGA chip.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a transmission delay testing method and device based on an FPGA.
Background
The field Programmable Gate array (fpga) is a semiconductor device, and includes some reprogrammable logic modules, which mainly includes the following three parts: configurable logic block CLB, input/output block IOB and programmable interconnection line (programmable interconnect). The FPGA designs a circuit with a hardware description language (such as Verilog), generates a bit stream file containing configuration information of all programmable logic modules through EDA software, and downloads the bit stream to a configuration memory unit inside the FPGA to complete configuration of CLBs, IOBs, programmable interconnection lines and the like, which is a mainstream technology of modern IC design verification.
Each programmable logic module in the FPGA, such as a CLB, an IOB, a programmable interconnection line, and the like, has a signal transmission delay, and the delay of the modules changes with the manufacturing process of the FPGA chip, the working voltage, the temperature, and the like, which causes difficulty in accurately calculating the signal transmission delay in the FPGA chip. EDA software must meet the timing constraints of the user to convert the user's design into the correct FPGA bitstream configuration information. Generally, a manufacturer measures and evaluates the transmission delay of the FPGA, a maximum value of the transmission delay is provided in a product manual, and a user performs design and development according to the maximum value to ensure that the timing sequence of the FPGA is also converged under other operating environments.
Generally, a manufacturer roughly evaluates transmission delay information of an FPGA by a simulation method in consideration of the worst condition to ensure that the produced FPGA can correctly operate, and the maximum transmission delay information obtained by simulation has a large safety margin compared with the actual transmission delay information, which results in that the FPGA chip cannot fully exert its own performance. In addition, if the set simulation condition is wrong, the obtained delay information may be greatly different from the actual delay information, so that the analysis result of the EDA software is inconsistent with the actual operation result.
Disclosure of Invention
The invention provides a transmission delay testing method and device based on an FPGA (field programmable gate array), and aims to solve the technical problem that the FPGA chip cannot give full play to the use performance because the maximum transmission delay information obtained based on the worst condition simulation has larger safety margin compared with the actual transmission delay information in the prior art.
In order to solve the technical problems, the invention adopts the following technical scheme:
the invention provides a transmission delay testing method of an FPGA (field programmable gate array), which comprises the following steps of:
the first D trigger is driven by a first clock to alternately output a low level signal and a high level signal, and the second D trigger is driven by a second clock to receive the signal output by the first D trigger; the period of the first clock is T1, the period of the second clock is T2, and T1 is greater than T2;
the control counter counts signals output by the second clock by taking the time when the effective clock edges of the first clock and the second clock determined by the edge synchronous detection unit are aligned as the counting starting time and the time when the second D trigger determined by the signal receiving determination unit continuously receives the signal sent by the first D trigger and is terminated as the counting termination time;
and determining the transmission delay to be measured of the path to be measured between the first D flip-flop and the second D flip-flop according to the phase difference of the first clock and the second clock determined by the counting of the counter and T1.
Further, the first clock, the second clock, the first D flip-flop, the second D flip-flop, the counter, the edge detection unit and the signal receiving determination unit are integrated in a single FPGA chip.
Further, the edge synchronization detecting unit includes: the third D trigger and the fourth D trigger are respectively driven by a first clock and a second clock;
the controlling the counter to count the signals output by the second clock by using the time when the effective clock edges of the first clock and the second clock determined by the edge synchronization detecting unit are aligned as the counting starting time and by using the time when the second D flip-flop determined by the signal receiving determining unit continuously receives the signal sent by the first D flip-flop as the counting ending time includes:
the signals output by the third D trigger and the fourth D trigger are respectively received by the fifth D trigger, and when the fifth D trigger moves forward along with the effective clock edge of the second clock and controls the signal output by the fifth D trigger to be inverted from a high level signal to a low level signal according to the received signals, the current moment is determined as the moment when the effective clock edges of the first clock and the second clock are aligned;
and controlling the counter to count the signals output by the second clock by taking the time when the effective clock edges of the first clock and the second clock are aligned as a counting starting time and the time when the second D trigger determined by the signal receiving and determining unit continuously receives the signal sent by the first D trigger and is terminated as a counting terminating time.
Further, the signal reception determination unit includes: the exclusive-or gate and a sixth D flip-flop which receives a signal output by the exclusive-or gate, wherein the sixth D flip-flop is driven by the second clock;
the controlling the counter to count the signals output by the second clock by using the time when the effective clock edges of the first clock and the second clock determined by the edge synchronization detecting unit are aligned as the counting starting time and by using the time when the second D flip-flop determined by the signal receiving determining unit continuously receives the signal sent by the first D flip-flop as the counting ending time includes:
controlling the counter to start counting the signals output by the second clock by taking the time when the effective clock edges of the first clock and the second clock determined by the edge synchronous detection unit are aligned as a counting starting time;
receiving a D port signal and a Q port signal of a second D trigger from the second D trigger through the XOR gate, and determining the current moment as the moment when the second D trigger continuously receives the signal sent by the first D trigger and terminates when a sixth D trigger receives a high level signal output by the XOR gate and is triggered by a second clock to output the high level signal;
and controlling the counter to stop counting the signals output by the second clock by taking the time when the second D trigger continuously receives the signal sent by the first D trigger as the counting termination time.
Furthermore, the controlling the counter to count the signals output by the second clock by using the time when the effective clock edges of the first clock and the second clock determined by the edge synchronization detecting unit are aligned as the counting start time and by using the time when the second D flip-flop determined by the signal receiving determining unit continuously receives the signal sent by the first D flip-flop as the counting end time includes:
under the condition that switches connected to two ends of a path to be detected between a first D trigger and a second D trigger are opened and closed, a counter is controlled, the time when effective clock edges of a first clock and an effective clock edge of a second clock are aligned and determined by an edge synchronous detection unit is taken as a counting starting time, the time when a signal sent by the first D trigger and continuously received by the second D trigger and determined by a signal receiving and determining unit is taken as a counting ending time, signals output by the second clock are counted, and a first count and a second count are obtained;
determining the transmission delay to be measured of the path to be measured between the first D flip-flop and the second D flip-flop according to the phase difference of the first clock and the second clock determined by the count of the counter and T1 includes:
determining a first transmission delay between the first D flip-flop and the second D flip-flop according to a first phase difference of the first clock and the second clock determined by the first count and T1, and determining a second transmission delay between the first D flip-flop and the second D flip-flop according to a second phase difference of the first clock and the second clock determined by the second count and T1;
and determining the difference value of the first transmission delay and the second transmission delay as the transmission delay to be measured of the path to be measured.
The invention provides a transmission delay testing device based on FPGA, comprising: the device comprises a first clock, a second clock, a first D trigger, a second D trigger, a counter, an edge synchronous detection unit and a signal receiving and determining unit, wherein a path to be detected is accessed between the first D trigger and the second D trigger; the Q port of the first D flip-flop is connected back to the D port through an inverter, the period of the first clock is T1, the period of the second clock is T2, and T1 is larger than T2;
the first clock is used for driving the first D trigger to alternately output a low level signal and a high level signal;
the second clock is used for driving the second D trigger to receive the signal output by the first D trigger;
the edge synchronous detection unit is used for determining the time when the effective clock edges of the first clock and the second clock are aligned;
the signal receiving determining unit is used for determining the time when the second D trigger continuously receives the signal sent by the first D trigger and is terminated;
the counter is used for counting the signals output by the second clock by taking the time determined by the edge synchronous detection unit as the counting starting time and taking the time determined by the signal receiving determination unit as the counting ending time; the count of the counter is used for determining the phase difference between the first clock and the second clock, the phase difference, and the T1 is used for determining the transmission delay to be measured of the path to be measured.
Further, the first clock, the second clock, the first D flip-flop, the second D flip-flop, the counter, the edge detection unit and the signal receiving determination unit are integrated in a single FPGA chip.
Further, the edge synchronization detecting unit includes: the third D trigger and the fourth D trigger are respectively driven by a first clock and a second clock; q ports of the third D flip-flop and the fourth D flip-flop are connected back to the D port through an inverter, and a D port and a CLK port of the fifth D flip-flop are respectively connected into the Q ports of the third D flip-flop and the fourth D flip-flop;
the fifth D trigger is used for respectively receiving the signals output by the third D trigger and the fourth D trigger and controlling the signals output by the fifth D trigger according to the received signals along with the forward movement of the effective clock edge of the second clock; the time when the signal output by the fifth D flip-flop is flipped from the high level signal to the low level signal is used to indicate the time when the valid clock edges of the first clock and the second clock are aligned.
Further, the signal reception determination unit includes: the exclusive-or gate and a sixth D flip-flop which receives a signal output by the exclusive-or gate, wherein the sixth D flip-flop is driven by the second clock; the exclusive-OR gate is respectively connected to a D port and a Q port of the second D trigger;
the exclusive-or gate is used for receiving a D port signal and a Q port signal of the second D flip-flop from the second D flip-flop and outputting a high-level signal when the D port signal and the Q port signal are different;
the sixth D flip-flop is used for receiving the high-level signal output by the exclusive-OR gate and outputting the high-level signal by being triggered by the second clock; the time when the sixth D flip-flop outputs the high level signal is used to indicate the time when the second D flip-flop continuously receives the signal sent by the first D flip-flop.
Still further, still include: switches connected to two ends of a path to be detected between the first D trigger and the second D trigger;
the counter is used for counting the signals output by the second clock by taking the time determined by the edge synchronous detection unit as the counting starting time and the time determined by the signal receiving determination unit as the counting ending time under the conditions that the switch is opened and closed respectively to obtain a first count and a second count; the first count and the second count are respectively used for determining a first phase difference and a second phase difference between the first clock and the second clock, the first phase difference and the second phase difference are respectively used for determining a first transmission delay and a second transmission delay between the first D trigger and the second D trigger with T1, and the difference value of the first transmission delay and the second transmission delay is the transmission delay to be measured of the path to be measured.
The invention has the beneficial effects that:
the invention provides a transmission delay testing method and a device based on FPGA (field programmable gate array), aiming at the defect that the maximum transmission delay information obtained based on worst condition simulation in the prior art has larger safety margin compared with the actual transmission delay information, so that an FPGA chip can not fully exert the service performance, the transmission delay testing method based on FPGA comprises the following steps: the first D trigger is driven by a first clock to alternately output a low level signal and a high level signal, and the second D trigger is driven by a second clock to receive the signal output by the first D trigger; the period of the first clock is T1, the period of the second clock is T2, and T1 is greater than T2; the control counter counts signals output by the second clock by taking the time when the effective clock edges of the first clock and the second clock determined by the edge synchronous detection unit are aligned as the counting starting time and the time when the second D trigger determined by the signal receiving determination unit continuously receives the signal sent by the first D trigger and is terminated as the counting termination time; and determining the transmission delay to be measured of the path to be measured between the first D flip-flop and the second D flip-flop according to the phase difference of the first clock and the second clock determined by the counting of the counter and T1. The two clock phases which are continuously tightened are simulated through the two clocks with different periods, the phase difference of the two clocks in the time interval from the alignment of the effective clock edges of the two clocks to the acquisition of the fast clock to the acquisition of the slow clock signal is determined according to the period of the slow clock, the transmission delay of the circuit to be tested is effectively improved, the design margin can be reasonably reduced when a user applies the FPGA, and the use performance of the FPGA chip can be fully exerted.
Drawings
Fig. 1 is a basic flowchart of a transmission delay testing method according to an embodiment of the present invention;
FIG. 2 is a waveform simulation diagram of an edge synchronization detecting unit according to an embodiment of the present invention;
fig. 3 is a basic flowchart of a transmission delay testing method according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a transmission delay testing apparatus according to a third embodiment of the present invention;
fig. 5 is a schematic structural diagram of an edge synchronization detecting unit according to a third embodiment of the present invention;
fig. 6 is a schematic waveform diagram according to a third embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention will now be further explained by means of embodiments in conjunction with the accompanying drawings.
The first embodiment is as follows:
in order to solve the defect that the maximum transmission delay information obtained based on the worst condition simulation has a larger safety margin compared with the actual condition in the prior art, so that the FPGA chip cannot fully exert the use performance, the present embodiment provides a transmission delay test method based on the FPGA, and as shown in fig. 1, the transmission delay test method is a basic flow chart of the transmission delay test method based on the FPGA provided in the present embodiment, and specifically includes the following steps:
s101, driving a first D trigger to alternately output a low-level signal and a high-level signal through a first clock, and driving a second D trigger to receive a signal output by the first D trigger through a second clock; the first clock has a period of T1, the second clock has a period of T2, and T1 is greater than T2.
Specifically, in the present embodiment, two clocks with different periods are input, and an absolute value of a difference between the periods of the two clocks is the transmission delay test accuracy in the present embodiment, where the period T1 of the first clock CLK1 is relatively large and is a slow clock, and the period T2 of the second clock CLK2 is relatively small and is a fast clock, and where an absolute value of approximately T1-T2 is sufficiently small, a high transmission delay test accuracy can be achieved. In addition, in the embodiment, two clocks respectively drive one D flip-flop (data flip-flop or delayfip-flop), the D flip-flop has a data input port (D port), a data latch output port (Q port), and a clock input port (CLK port), where CLK1 is used to drive a first D flip-flop FF1 to output a signal, and CLK2 is used to drive a second D flip-flop FF2 to receive data output by a first D flip-flop FF1, and the operating principle of the D flip-flop is as follows: when the rising edge of the clock signal arrives, the data of the D port will be transferred to the Q port and Q non-port, where the Q port and Q non-port are identical in characteristics except for inversion. The CLK1 and the CLK2 in this embodiment output clock signals simultaneously, and the phase difference between the two signals is T1-T2, so that two clock phases which are tightened continuously are simulated through the CLK1 and the CLK 2. It should be noted that, in this embodiment, the Q port of the first D flip-flop FF1 is connected back to the D port of the flip-flop through an inverter, and the inverter is used as a shaping circuit to flip the phase of the signal by 180 degrees, so that the first D flip-flop FF1 can output signals 0 and 1 alternately, that is, a low level signal and a high level signal.
It should be noted that, in this embodiment, the paths to be tested are accessed in the FF1 and the FF2, the signal output by the Q port of the FF1 reaches the D port of the FF2 through a period of delay to be received, and the transmission delay of the signal in the path is the transmission delay (propagation delay) to be tested.
And S102, controlling the counter to count the signals output by the second clock by taking the time when the effective clock edges of the first clock and the second clock determined by the edge synchronous detection unit are aligned as a counting starting time and taking the time when the second D trigger determined by the signal receiving determination unit continuously receives the signal sent by the first D trigger as a counting ending time.
Specifically, the edge synchronization detection, i.e. the detection of the rising edge and the falling edge, in this embodiment, the edge synchronization detection unit is controlled to detect whether the effective clock edges, i.e. the rising edges, of the two clocks CLK1 and CLK2 are aligned, the edge synchronization detection unit is used in a principle that the effective clock edge of the clock CLK2 with the faster frequency is used to acquire the current value of the clock CLK1 with the slower frequency, i.e. the clock 2 is used to acquire the level value of the clock CLK1, the edge synchronization detection unit will periodically output 0 and 1 values with the same number as the effective clock edge of the clock CLK2, the number of 0 and 1 output per segment is T1/2/(T1-T2), when the effective clock edges of the two clocks are aligned, the output of the edge synchronous detection unit changes from 1 jump to 0, namely, the output is overturned from high level to low level, and outputs a pulse of a falling edge, when the two clocks have a phase difference of T1-T2.
Optionally, the edge synchronization detecting unit includes: the third D trigger and the fourth D trigger are respectively driven by a first clock and a second clock; and the fifth D flip-flop receives signals output by the third D flip-flop and the fourth D flip-flop respectively, and determines that the current moment is the moment when the effective clock edges of the first clock and the second clock are aligned when the fifth D flip-flop controls the signal output by the fifth D flip-flop to be turned from a high level signal to a low level signal along with the forward movement of the effective clock edge of the second clock according to the received signals.
Specifically, the edge synchronization detecting unit in this embodiment includes three D flip-flops, the Q ports of the third D flip-flop FF3 and the fourth D flip-flop FF4 are both connected back to the D port through an inverter, and the D port and the CLK port of the fifth D flip-flop FF5 are connected to the Q ports of the third D flip-flop FF3 and the fourth D flip-flop FF4, respectively. Of these, FF3 and FF4 are driven using CLK1 and CLK2, respectively, and the inverter is used as a frequency divider in order to be able to switch the clock signal of the clock tree into the D port of the D flip-flop. While FF5 has its CLK port connected to the Q port of FF4 and its D port connected to the Q port of FF3, i.e., FF5 uses the divided clock CLK2 to capture the signal of clock CLK1, it is understood that the alignment of the active clock edges of CLK1 and CLK2 and the alignment of the active clock edges of divided clocks CLK1 'and CLK 2' are the same. Fig. 2 is a waveform simulation diagram of the edge synchronization detecting unit provided in this embodiment, CLK1 'and CLK 2' are clocks obtained by dividing CLK1 and CLK2, and as shown in fig. 2, as the phase shift of CLK1 and CLK2 is tightened with time, FF5 periodically outputs 0 and 1 signals with equal number, and when the output jumps from 1 to 0, it can be considered that the effective clock edges of the two clocks are aligned.
In addition, the phase difference between CLK1 and CLK2 increases by T1-T2 every time a cycle passes, so that CLK1 and CLK2 have a phase shift that steps by T1-T2 over time, and then as the phase between CLK1 and CLK2 is continuously tightened, there must be a certain time when the signal output by the first D flip-flop driven by CLK1 is not captured by the second D flip-flop driven by CLK 2.
Optionally, the signal receiving determining unit includes: the exclusive-or gate and a sixth D flip-flop which receives a signal output by the exclusive-or gate, wherein the sixth D flip-flop is driven by the second clock; and D port signals and Q port signals of the second D flip-flop are received from the second D flip-flop through the XOR gate, and when the sixth D flip-flop receives a high-level signal output by the XOR gate and is triggered by the second clock to output the high-level signal, the current moment is determined to be the moment when the second D flip-flop continuously receives the signal sent by the first D flip-flop and terminates.
Specifically, the xor gate is respectively connected to the D port and the Q port of the second D flip-flop FF2, and is used to test whether the signal of the D port of the second D flip-flop FF2 and the signal of the Q port are consistent, if so, the xor gate outputs a low level signal, otherwise, the xor gate outputs a high level signal. In addition, in order to avoid ambiguity when the FF2 determines the time when the signal output by the FF1 is not received directly according to the signal output by the xor gate, the sixth D flip-flop FF6 in this embodiment is also driven by the CLK2, and is configured to receive the output signal of the preceding xor gate, and when receiving the high level signal output by the xor gate and receiving the clock signal output by the CLK2, the FF6 is triggered to output a high level signal for indicating that the FF2 will not capture the signal output by the FF1, and conversely, when the FF6 outputs a low level signal, indicating that the FF2 can still correctly capture the signal output by the FF 1. Therefore, when the signals of the D port and the Q port of the FF2 are different, that is, the signal output by the FF1 just reaches the D port of the FF2 but cannot be collected by the FF2, a high level signal is generated by the xor gate, and a high level pulse is output by the Q port of the FF6 after one clock cycle of the CLK 2.
It should be noted that in the present embodiment, a counter is introduced, which records that from the time when the effective clock edges of the two clocks are aligned, the FF6 outputs a high-level pulse to be turned off, the CLK2 signal during this period is counted, and every time one cycle of the CLK2 passes, the phase shift between the CLK1 and the CLK2 can be determined to be tightened by T1-T2, and the number counted by the counter is the number of phase shifts during this period.
And S103, determining the transmission delay to be measured of the path to be measured between the first D trigger and the second D trigger according to the phase difference between the first clock and the second clock determined by the counting of the counter and T1.
Specifically, assuming that the count output by the counter is N when FF6 outputs a high-level pulse, and since FF6 outputs a signal of one cycle on FF2, the actual number of phase shifts is N-1, that is, N-1 phase shifts are actually performed, and since there is a phase difference between the two clocks at the time when the effective clock edges of the two clocks of CLK1 and CLK2 are aligned, the total phase difference of the two clocks in the time interval can be determined to be N (T1-T2) according to the actual number of phase shifts and the steps T1-T2 therebetween, and then the transmission delay of the path to be measured from FF1 to FF2 can be calculated to be T1-N (T1-T2).
It should be noted that, in a preferred embodiment, the first clock, the second clock, the first D flip-flop, the second D flip-flop, the counter, the edge detection unit, and the signal reception determination unit in this embodiment are integrated in a single FPGA chip, that is, the transmission delay of the circuit to be tested can be implemented by using available logic resources inside the FPGA chip, which is simple to implement and can save resources.
Optionally, the counter is controlled to count signals output by the second clock by taking a time when effective clock edges of the first clock and the second clock determined by the edge synchronization detection unit are aligned as a counting start time and a time when the second D flip-flop determined by the signal receiving determination unit continuously receives a signal sent by the first D flip-flop and terminates as a counting end time under the condition that switches connected to two ends of a path to be measured between the first D flip-flop and the second D flip-flop are opened and closed, respectively, so as to obtain a first count and a second count; determining a first transmission delay between the first D flip-flop and the second D flip-flop according to a first phase difference of the first clock and the second clock determined by the first count and T1, and determining a second transmission delay between the first D flip-flop and the second D flip-flop according to a second phase difference of the first clock and the second clock determined by the second count and T1; and determining the difference value of the first transmission delay and the second transmission delay as the transmission delay to be measured of the path to be measured.
Specifically, in some embodiments, a switch may be further connected to two ends of the path to be tested, and two different test environments may be simulated by opening and closing the switch, so that the counting in the counting time interval is performed under two conditions of opening and closing the switch, two phase differences under two conditions are obtained, and the transmission delay under two conditions is obtained, and finally, the difference of the transmission delay under two different conditions may be determined as the transmission delay of the path to be tested, so as to further improve the test accuracy of the transmission delay of the path to be tested.
The invention provides a transmission delay test method based on FPGA, which simulates two clock phases which are continuously tightened by two clocks with different periods, determines the transmission delay of a circuit to be tested according to the phase difference of the two clocks in a time interval from the alignment of effective clock edges of the two clocks to the acquisition of a fast clock to the acquisition of a slow clock signal and the period of the slow clock, effectively improves the accuracy of the transmission delay test, enables a user to reasonably reduce the design margin when the FPGA is applied, and can fully exert the use performance of an FPGA chip.
Example two:
in order to better understand the present invention, this embodiment describes a transmission delay testing method based on an FPGA with a specific example, and fig. 3 is a detailed flowchart of the transmission delay testing method based on the FPGA according to the second embodiment of the present invention, where the transmission delay testing method includes:
s301, driving a first D trigger to alternately output a low-level signal and a high-level signal through a first clock, and driving a second D trigger to receive a signal output by the first D trigger through a second clock; the first clock has a period of T1, the second clock has a period of T2, and T1 is greater than T2.
In this embodiment, two clocks with different periods are input, and an absolute value of a difference between the periods of the two clocks is also the transmission delay test accuracy in this embodiment, where the period T1 of the first clock CLK1 is relatively large and is a slow clock, and the period T2 of the second clock CLK2 is relatively small and is a fast clock, and where the absolute values of T1-T2 are approximately small enough, the high transmission delay test accuracy can be achieved. For example, in the present embodiment, the periods of CLK1 and CLK2 are set to 100.00ns and 99.99ns, respectively, the test accuracy is 0.01ns, in the present embodiment, CLK1 and CLK2 output clock signals simultaneously, the phase difference between the two signals is T1-T2, and it can be known that the step size of clock phase shift is 0.01ns, so that two clock phases which are continuously tightened are simulated through CLK1 and CLK 2.
S302, controlling switches connected to two ends of a path to be tested between the first D trigger and the second D trigger to be disconnected, and executing S304.
And S303, controlling switches connected to two ends of a path to be detected between the first D trigger and the second D trigger to be closed, and executing S304.
In this embodiment, a switch is connected to both ends of the path to be tested, two different test environments can be simulated by opening and closing the switch, and the subsequent counting process is executed under two conditions of opening and closing the switch, so that the test accuracy of the transmission delay of the path to be tested can be further improved.
S304, respectively receiving signals output by a third D trigger and a fourth D trigger through a fifth D trigger, and determining the current moment as the moment when the effective clock edges of the first clock and the second clock are aligned when the fifth D trigger controls the signal output by the fifth D trigger to be turned from a high-level signal to a low-level signal along with the forward movement of the effective clock edge of the second clock according to the received signals; the third D flip-flop and the fourth D flip-flop are driven by the first clock and the second clock, respectively.
And S305, controlling the counter to start counting the signals output by the second clock by taking the time when the effective clock edges of the first clock and the second clock are aligned as the counting starting time.
In this embodiment, an edge synchronization detection unit formed by the third D flip-flop FF3, the fourth D flip-flop FF4, and the fifth D flip-flop FF5 is used to detect whether the effective clock edges of the two clocks of CLK1 and CLK2 are aligned, the adopted method is to use CLK2 to acquire the level value of CLK1, as the effective clock edge of CLK2 moves forward, the FF5 periodically outputs 0 and 1 values with equal number, and when the output jumps from 1 to 0, it can be considered that the effective clock edges of the two clocks are aligned at this time, which is the counting start time.
S306, receiving a D port signal and a Q port signal of a second D trigger from the second D trigger through the XOR gate, and determining that the current moment is the moment when the second D trigger continuously receives the signal sent by the first D trigger and terminates when a sixth D trigger receives a high level signal output by the XOR gate and is triggered by a second clock to output the high level signal; the signal output by the exclusive-or gate is received by the sixth D flip-flop, which is driven by the second clock.
And S307, controlling the counter to stop counting the signals output by the second clock by taking the time when the second D trigger continuously receives the signal sent by the first D trigger as the counting termination time, and respectively obtaining a first counting under the condition that the switch is opened and a second counting under the condition that the switch is closed.
Every time a cycle passes, the phase difference between CLK1 and CLK2 increases by T1-T2, so that CLK1 and CLK2 have a phase shift that steps to T1-T2 over time, and then as the phase between CLK1 and CLK2 is continuously tightened, there must be a certain time when the signal output by first D flip-flop FF1 driven by CLK1 is not picked up by second D flip-flop FF2 driven by CLK 2. In this embodiment, the D port and the Q port of the FF2 are respectively accessed through the xor gate to determine whether the signal of the D port of the FF2 and the signal of the Q port are consistent, if so, the xor gate outputs a low level signal, and if not, the xor gate outputs a high level signal. The sixth D flip-flop FF6 in this embodiment is also driven by CLK2, and when receiving the high level signal output by the xor gate and receiving the clock signal output by CLK2, the FF6 is triggered to output a high level signal, which is used to indicate that the FF2 will not collect the signal output by the FF1 at this time, which is the counting termination time.
Assuming that the count of the counter is N1 when FF6 outputs a high level signal when the switch is turned off, and the count of the counter is N2 when FF6 outputs a high level signal when the switch is turned off, since FF6 outputs a signal of one cycle previous to FF2, the actual number of phase shifts is N1-1 and N2-1, respectively, whereas there is a phase difference between the two clocks at the start of counting, so the total phase shift difference is N1 (T1-T2) and N2 (T1-T2), respectively, and the foregoing examples, i.e., 0.01N 1 and 0.01N 2, respectively, are continued.
And S308, determining a first transmission delay between the first D flip-flop and the second D flip-flop according to the first phase difference of the first clock and the second clock determined by the first counting and T1, and determining a second transmission delay between the first D flip-flop and the second D flip-flop according to the second phase difference of the first clock and the second clock determined by the second counting and T1.
S309, determining the difference value of the first transmission delay and the second transmission delay as the transmission delay to be detected of the path to be detected.
Continuing with the foregoing example, i.e., the first transmission delay is 100-0.01 × N1 when the switch is open and the second transmission delay is 100-0.01 × N2 when the switch is closed, so that the transmission delay to be measured of the path to be measured is an absolute value of 0.01 × N2-N1.
The invention provides a transmission delay test method based on FPGA, which simulates two clock phases which are continuously tightened by two clocks with different periods, determines the transmission delay of a circuit to be tested according to the phase difference of the two clocks in a time interval from the alignment of effective clock edges of the two clocks to the acquisition of a fast clock to the acquisition of a slow clock signal and the period of the slow clock, effectively improves the accuracy of the transmission delay test, enables a user to reasonably reduce the design margin when the FPGA is applied, and can fully exert the use performance of an FPGA chip.
Example three:
the embodiment provides a transmission delay testing device based on an FPGA, and specifically refers to fig. 4, including: a first clock 41, a second clock 42, a first D flip-flop 43, a second D flip-flop 44, a counter 45, an edge synchronization detection unit 46 and a signal reception determination unit 47, wherein a path to be tested 48 is connected between the first D flip-flop 43 and the second D flip-flop 44; the Q port of the first D flip-flop 43 is connected back to the D port through an inverter, the period of the first clock 41 is T1, the period of the second clock 42 is T2, and T1 is greater than T2; the first clock 41 is used for driving the first D flip-flop 43 to alternately output a low-level signal and a high-level signal; the second clock 42 is used for driving the second D flip-flop 44 to receive the signal output by the first D flip-flop 43; the edge synchronization detecting unit 46 is used for determining the time when the valid clock edges of the first clock 41 and the second clock 42 are aligned; the signal receiving determining unit 47 is configured to determine a time when the second D flip-flop 44 continuously receives the signal sent by the first D flip-flop 43; the counter 45 is configured to count the signals output by the second clock 42, with the time determined by the edge synchronization detection unit 46 as a count start time and the time determined by the signal reception determination unit 47 as a count end time; the count of the counter 45 is used to determine the phase difference between the first clock 41 and the second clock 42, the phase difference, and the T1 is used to determine the transmission delay to be measured of the path to be measured 48.
Specifically, in the present embodiment, two clocks with different cycles are input, and an absolute value of a difference between the cycles of the two clocks is the transmission delay test accuracy in the present embodiment, where the cycle T1 of the first clock 41 is relatively large and is a slow clock, and the cycle T2 of the second clock 42 is relatively small and is a fast clock, where an absolute value of approximately T1-T2 is sufficiently small, and a very high transmission delay test accuracy can be achieved. The first clock 41 and the second clock 42 in this embodiment output clock signals simultaneously, and the phases of the two clocks are different from each other by T1-T2, so that two tightening clock phases are simulated by the first clock 41 and the second clock 42. It should be noted that the Q port of the first D flip-flop 43 in this embodiment is connected back to the D port of the flip-flop through an inverter, so that the first D flip-flop 43 can output signals 0 and 1 alternately, that is, a low level signal and a high level signal. In addition, in the embodiment, the first D flip-flop 43 and the second D flip-flop 44 are connected to a path 48 to be measured, a signal output from the Q port of the first D flip-flop 43 reaches the D port of the second D flip-flop 44 after a period of delay, and is received, where the transmission delay of the signal in the path is transmission delay (propagation delay) to be measured.
In addition, in this embodiment, the edge synchronization detecting unit 46 is controlled to detect whether the effective clock edges, i.e. rising edges, of the first clock 41 and the second clock 42 are aligned, the edge synchronization detecting unit 46 is used in a principle that the effective clock edge of the clock second 42 with the faster frequency is used to acquire the current value of the clock first 41 with the slower frequency, i.e. the clock second 42 is used to acquire the level value of the first clock 41, the edge synchronization detecting unit 46 periodically outputs 0 and 1 values with the same number as the effective clock edge of the second clock 42, and when the effective clock edges of the two clocks are aligned, the output of the edge synchronization detecting unit 46 changes from 1 to 0, i.e. from high to low, and outputs a pulse with a falling edge, and the time is used as the starting time for detecting the number of phase shifts. And, every time a period passes, the phase difference between the first clock 41 and the second clock 42 increases by T1-T2, so that the first clock 41 and the second clock 42 have a phase shift of T1-T2 with the passage of time, then, as the phase between the first clock 41 and the second clock 42 is continuously tightened, there must be a certain time, the second D flip-flop 44 driven by the second clock 42 will not acquire the signal output by the first D flip-flop 43 driven by the first clock 41, so that the signal reception determining unit 47 detects the signal reception behavior of the second D flip-flop 44, and the determined time when the second D flip-flop 44 cannot acquire the signal output by the first D flip-flop 43 is taken as the termination time of the detected phase shift number.
It should be further noted that in the present embodiment, the transmission delay to be measured of the path to be measured 48 between the first D flip-flop 43 and the second D flip-flop 44 is determined according to the phase difference between the first clock 41 and the second clock 42 determined by the counting of the counter 45 and the T1. If the count of the counter is N, the transmission delay to be measured is T1-N (T1-T2).
It should be noted that, in a preferred embodiment, the first clock 41, the second clock 42, the first D flip-flop 43, the second D flip-flop 44, the counter 45, the edge synchronization detection unit 46, and the signal reception determination unit 47 in this embodiment are integrated in a single FPGA chip, that is, the transmission delay of the circuit to be tested 48 can be realized by using available logic resources inside the FPGA chip, which is simple to implement and can save resources.
In a preferred example of the present embodiment, please refer to fig. 5, fig. 5 is a schematic structural diagram of an edge synchronization detecting unit provided in the present embodiment, and the edge synchronization detecting unit 46 includes: a third D flip-flop 461, a fourth D flip-flop 462 and a fifth D flip-flop 463, the third D flip-flop 461 and the fourth D flip-flop 462 being driven by the first clock 41 and the second clock 42, respectively; the Q ports of the third D flip-flop 461 and the fourth D flip-flop 462 are both connected back to the D port through an inverter, and the D port and the CLK port of the fifth D flip-flop 463 are connected to the Q ports of the third D flip-flop 461 and the fourth D flip-flop 462, respectively. The fifth D flip-flop 463 is configured to receive signals output by the third D flip-flop 461 and the fourth D flip-flop 462 respectively, and control the output signal thereof according to the received signals as the effective clock edge of the second clock 42 moves forward; the timing at which the signal output by the fifth D flip-flop 463 is inverted from the high level signal to the low level signal is used to indicate the timing at which the effective clock edges of the first clock 41 and the second clock 42 are aligned.
In a preferred example of the present embodiment, please continue to refer to fig. 4, the signal receiving determining unit 47 includes: an exclusive or gate 471 and a sixth D flip-flop 472 receiving a signal output from the exclusive or gate 471, the sixth D flip-flop 472 being driven by the second clock 41; the exclusive or gate 471 is connected to the D port and the Q port of the second D flip-flop 44, respectively. The xor gate 471 is configured to receive a D port signal and a Q port signal of the second D flip-flop 44 from the second D flip-flop 44, and output a high level signal when the D port signal and the Q port signal are different; the sixth D flip-flop 472 is configured to receive the high level signal output by the xor gate 471 and output the high level signal triggered by the second clock 42; the time when the sixth D flip-flop 472 outputs the high level signal is used to indicate the time when the second D flip-flop 44 continuously receives the signal sent by the first D flip-flop 43.
In a preferred example of the present embodiment, please continue to refer to fig. 4, a switch 49 is further connected to two ends of a path 48 to be tested between the first D flip-flop 43 and the second D flip-flop 44 in the present embodiment, so that two different testing environments can be simulated by opening and closing the switch 49. The counter 45 is configured to count the signals output by the second clock 42 by using the time determined by the edge synchronization detecting unit 46 as a counting start time and the time determined by the signal reception determining unit 47 as a counting end time when the switch 49 is opened and closed, respectively, to obtain a first count and a second count; the first count and the second count are respectively used for determining a first phase difference and a second phase difference of the first clock 41 and the second clock 42, the first phase difference and the second phase difference are respectively used for determining a first transmission delay and a second transmission delay between the first D flip-flop 43 and the second D flip-flop 44 with the T1, and a difference value between the first transmission delay and the second transmission delay is a transmission delay to be measured of the path 48 to be measured.
As shown in fig. 6, which is a waveform diagram provided by the present embodiment, it can be seen that when the Q port output of the fifth D flip-flop in the edge synchronization detecting unit flips from high level to low level, the effective clock edges of the first clock and the second clock are aligned and correspond to T1 and T2 in the figure, respectively, and the phase difference between the two clocks is T1-T2. The time corresponding to T4 is the time when the first D flip-flop emits a signal, passes through the circuit to be tested, and arrives at the second D flip-flop right, at this time, the signals of the D port and the Q port of the second D flip-flop are different, a high level signal is generated through the xor gate, and a high level signal is output from the Q port of the sixth D flip-flop through one clock cycle of the second clock, where the time corresponds to the time of T3 in the figure. In the figure, N represents the number counted by counting the output signal of the second clock 42 between the times T1 and T3 by the counter.
The invention provides a transmission delay testing device based on FPGA, which simulates two clock phases which are continuously tightened by two clocks with different periods, determines the alignment time of effective clock edges of the two clocks by an edge synchronous detection unit, determines the time of a fast clock which can not acquire a slow clock signal by a signal receiving determination unit, calculates the phase difference of the two clocks according to the number counted by a counter in the time interval from the alignment of the effective clock edges of the two clocks to the alignment of the effective clock edges of the fast clock which can not acquire the slow clock signal, and determines the transmission delay of a circuit to be tested by combining the calculated phase difference with the period of the slow clock, thereby effectively improving the accuracy of transmission delay testing, leading a user to reasonably reduce the design margin when the FPGA is applied and fully playing the using performance of an FPGA chip.
The foregoing is a more detailed description of the present invention that is presented in conjunction with specific embodiments, and the practice of the invention is not to be considered limited to those descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. The transmission delay testing method based on the FPGA is characterized by comprising the following steps of:
the method comprises the steps that a first D trigger is driven by a first clock to alternately output a low-level signal and a high-level signal, and a second D trigger is driven by a second clock to receive a signal output by the first D trigger; the period of the first clock is T1, the period of the second clock is T2, and the T1 is greater than T2;
controlling a counter to count signals output by a second clock by taking the time when effective clock edges of the first clock and the second clock are aligned, which is determined by an edge synchronous detection unit, as a counting starting time and taking the time when a signal which is sent by the first D flip-flop and is continuously received by the second D flip-flop, which is determined by a signal receiving determination unit, as a counting ending time;
and determining the transmission delay to be measured of the path to be measured between the first D flip-flop and the second D flip-flop according to the phase difference between the first clock and the second clock determined by the counting of the counter and the T1.
2. The transmission delay test method of claim 1, wherein the first clock, the second clock, the first D flip-flop, the second D flip-flop, the counter, the edge synchronization detecting unit, and the signal reception determining unit are integrated in a single FPGA chip.
3. The transmission delay test method of claim 1, wherein the edge synchronization detecting unit comprises: a third D flip-flop, a fourth D flip-flop, and a fifth D flip-flop, the third D flip-flop and the fourth D flip-flop driven by the first clock and the second clock, respectively;
the control counter takes the time when the effective clock edges of the first clock and the second clock determined by the edge synchronization detection unit are aligned as a counting starting time, and takes the time when the second D flip-flop determined by the signal receiving determination unit continuously receives the signal sent by the first D flip-flop as a counting ending time, and counting the signal output by the second clock includes:
respectively receiving signals output by the third D flip-flop and the fourth D flip-flop through the fifth D flip-flop, and determining that the current moment is the moment when the effective clock edges of the first clock and the second clock are aligned when the fifth D flip-flop controls the signal output by the fifth D flip-flop to be turned from a high level signal to a low level signal along with the forward movement of the effective clock edge of the second clock according to the received signals;
and controlling the counter to count the signals output by the second clock by taking the time when the effective clock edges of the first clock and the second clock are aligned as a counting starting time and taking the time when the second D trigger continuously receives the signal sent by the first D trigger and determined by the signal receiving and determining unit as a counting ending time.
4. The transmission delay test method of claim 1, wherein the signal reception determining unit comprises: an exclusive-or gate and a sixth D flip-flop receiving a signal output by the exclusive-or gate, the sixth D flip-flop being driven by the second clock;
the control counter takes the time when the effective clock edges of the first clock and the second clock determined by the edge synchronization detection unit are aligned as a counting starting time, and takes the time when the second D flip-flop determined by the signal receiving determination unit continuously receives the signal sent by the first D flip-flop as a counting ending time, and counting the signal output by the second clock includes:
controlling a counter to start counting signals output by the second clock by taking the time when the effective clock edges of the first clock and the second clock are aligned, which is determined by the edge synchronous detection unit, as a counting starting time;
receiving a D port signal and a Q port signal of the second D flip-flop from the second D flip-flop through the xor gate, and determining that the current time is the time when the second D flip-flop continuously receives the signal sent by the first D flip-flop and terminates when the sixth D flip-flop receives the high level signal output by the xor gate and is triggered by the second clock to output the high level signal;
and controlling the counter to stop counting the signals output by the second clock by taking the time when the second D trigger continuously receives the signal sent by the first D trigger as the counting termination time.
5. The transmission delay test method according to any one of claims 1 to 4, wherein the controlling the counter to count the signals output by the second clock by taking the time when the valid clock edges of the first clock and the second clock are aligned as a count start time and the time when the second D flip-flop continues to receive the signal sent by the first D flip-flop as a count end time, which are determined by the signal receiving determination unit, as a count end time, comprises:
under the condition that switches connected to two ends of a path to be measured between the first D trigger and the second D trigger are opened and closed respectively, the counter is controlled to count signals output by the second clock by taking the time when effective clock edges of the first clock and the second clock are aligned, which is determined by the edge synchronous detection unit, as a counting starting time and the time when the second D trigger continuously receives a signal sent by the first D trigger and is terminated, which is determined by the signal receiving determination unit, as a counting terminating time, so that a first count and a second count are obtained;
the determining, according to the phase difference between the first clock and the second clock determined by the counting of the counter and the T1, a transmission delay to be measured of a path to be measured between the first D flip-flop and the second D flip-flop comprises:
determining a first transmission delay between the first D flip-flop and the second D flip-flop according to a first phase difference of the first clock and the second clock determined by the first count and the T1, and determining a second transmission delay between the first D flip-flop and the second D flip-flop according to a second phase difference of the first clock and the second clock determined by the second count and the T1;
and determining the difference value of the first transmission delay and the second transmission delay as the transmission delay to be detected of the path to be detected.
6. The utility model provides a transmission delay testing arrangement based on FPGA which characterized in that includes: the device comprises a first clock, a second clock, a first D trigger, a second D trigger, a counter, an edge synchronous detection unit and a signal receiving and determining unit, wherein a path to be detected is accessed between the first D trigger and the second D trigger; the Q port of the first D flip-flop is connected back to the D port through an inverter, the period of the first clock is T1, the period of the second clock is T2, and the T1 is larger than T2;
the first clock is used for driving the first D flip-flop to alternately output a low-level signal and a high-level signal;
the second clock is used for driving the second D flip-flop to receive the signal output by the first D flip-flop;
the edge synchronization detection unit is used for determining the time when the effective clock edges of the first clock and the second clock are aligned;
the signal receiving determining unit is used for determining the time when the second D trigger continuously receives the signal sent by the first D trigger and is terminated;
the counter is used for counting the signals output by the second clock by taking the time determined by the edge synchronous detection unit as a counting starting time and taking the time determined by the signal receiving determination unit as a counting ending time; the count of the counter is used for determining the phase difference between the first clock and the second clock, and the phase difference and the T1 are used for determining the transmission delay to be measured of the path to be measured.
7. The transmission delay test apparatus of claim 6, wherein the first clock, the second clock, the first D flip-flop, the second D flip-flop, the counter, the edge synchronization detection unit, and the signal reception determination unit are integrated in a single FPGA chip.
8. The transmission delay test apparatus of claim 6, wherein the edge synchronization detecting unit comprises: a third D flip-flop, a fourth D flip-flop, and a fifth D flip-flop, the third D flip-flop and the fourth D flip-flop driven by the first clock and the second clock, respectively; the Q ports of the third D flip-flop and the fourth D flip-flop are connected back to the D port through an inverter, and the D port and the CLK port of the fifth D flip-flop are respectively connected into the Q ports of the third D flip-flop and the fourth D flip-flop;
the fifth D flip-flop is used for respectively receiving the signals output by the third D flip-flop and the fourth D flip-flop, and controlling the signals output by the fifth D flip-flop according to the received signals along with the forward movement of the effective clock edge of the second clock; the time when the signal output by the fifth D flip-flop is turned from a high level signal to a low level signal is used to indicate the time when the active clock edges of the first clock and the second clock are aligned.
9. The transmission delay test apparatus of claim 6, wherein the signal reception determining unit comprises: an exclusive-or gate and a sixth D flip-flop receiving a signal output by the exclusive-or gate, the sixth D flip-flop being driven by the second clock; the exclusive-or gate is respectively connected to a D port and a Q port of the second D trigger;
the exclusive-or gate is used for receiving a D port signal and a Q port signal of the second D flip-flop from the second D flip-flop and outputting a high-level signal when the D port signal and the Q port signal are different;
the sixth D flip-flop is used for outputting a high-level signal when receiving the high-level signal output by the exclusive-OR gate and being triggered by the second clock; and the time when the sixth D trigger outputs a high-level signal is used for indicating the time when the second D trigger continuously receives the signal sent by the first D trigger and is terminated.
10. The transmission delay test apparatus according to any one of claims 6 to 9, further comprising: switches connected to two ends of a path to be tested between the first D trigger and the second D trigger;
the counter is used for counting the signals output by the second clock by taking the time determined by the edge synchronous detection unit as a counting starting time and the time determined by the signal receiving determination unit as a counting ending time under the condition that the switch is opened and closed respectively to obtain a first count and a second count; the first count and the second count are respectively used for determining a first phase difference and a second phase difference between the first clock and the second clock, the first phase difference and the second phase difference are respectively used for determining a first transmission delay and a second transmission delay between the first D flip-flop and the second D flip-flop with the T1, and a difference value between the first transmission delay and the second transmission delay is a to-be-detected transmission delay of the to-be-detected path.
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| US11989148B2 (en) | 2020-12-30 | 2024-05-21 | Stmicroelectronics International N.V. | Data bridge for interfacing source synchronous datapaths with unknown clock phases |
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| CN113188372B (en) * | 2021-04-02 | 2022-08-30 | 绵阳慧视光电技术有限责任公司 | Method and device for measuring processing delay time of optical seeker |
| CN113377060B (en) * | 2021-08-13 | 2021-11-09 | 成都博宇利华科技有限公司 | Method for acquiring sampling time of each sampling point in signal acquisition system |
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