CN112816858B

CN112816858B - Digital circuit delay test method, test circuit and integrated circuit chip

Info

Publication number: CN112816858B
Application number: CN202011636594.7A
Authority: CN
Inventors: 马淑彬; 湛伟; 夏明刚; 张俐; 丛伟林
Original assignee: Chengdu Hua Microelectronics Technology Co ltd
Current assignee: Chengdu Hua Microelectronics Technology Co ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2022-09-16
Anticipated expiration: 2040-12-31
Also published as: CN112816858A

Abstract

A digital circuit delay test method, a test circuit and an integrated circuit chip relate to the integrated circuit technology. The digital circuit delay testing method comprises the following steps: 1) sending test data to a data port of a module to be tested at the initial moment, wherein the time length increment between two adjacent test data is t; 2) comparing the output data and the input data of the module to be tested, and outputting an excitation signal when the output data and the input data are inconsistent; 3) and counting the sending times of the test data between the starting moment and the sending moment of the excitation signal, and calculating the time delay of the module to be tested by combining the t value. The invention reduces the influence of chip packaging, input and output circuits, PCB wiring and the like on the testing delay precision.

Description

Digital circuit delay test method, test circuit and integrated circuit chip

Technical Field

The present invention relates to integrated circuit technology.

Background

In the prior art, the measurement of the digital circuit delay is based on an external measurement circuit, the precision is restricted by the external circuit, and the requirement of on-site real-time measurement cannot be met.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a digital circuit delay testing technology built in a chip, which can accurately test the delay performance of a functional module.

The technical scheme adopted by the invention for solving the technical problem is that the digital circuit delay testing method is characterized by comprising the following steps:

1) sending test data to a data port of a module to be tested at an initial moment, wherein the time increment of two adjacent intervals is t, and the interval is the time between two adjacent test data;

2) comparing the output data and the input data of the module to be tested, and outputting an excitation signal when the output data and the input data are inconsistent; 3) and counting the sending times of the test data between the starting moment and the sending moment of the excitation signal, and calculating the time delay of the module to be tested by combining the t value.

The invention also provides a digital circuit delay test circuit, which comprises the following parts:

the adjustable delay module is used for generating a variable clock signal with adjacent cycle increment of t and outputting increment information to the statistical module;

the test data generator is connected with the adjustable delay module and used for sending test data to the module to be tested when receiving the output signal excitation edge of the adjustable delay module;

the first input end of the data comparator is connected with the data output end of the module to be tested, the second input end of the data comparator is connected with the output end of the test data generator, and the output end of the data comparator is connected with the control end of the statistical module;

and the statistical module is used for counting the sending times of the test data between the starting moment and the moment when the control end receives the excitation signal.

The data generator is a random number generator.

The invention also provides an integrated circuit chip with the built-in digital circuit delay test circuit.

The invention can accurately test the time delay of the internal functional module of the chip, reduces the dependence on external instruments by adopting a built-in mode, and reduces the influence of chip packaging, input and output circuits, PCB routing and the like on the test time delay precision.

Drawings

FIG. 1 is a schematic diagram of a test circuit according to the present invention.

Fig. 2 is a timing diagram of the present invention.

Fig. 3 is a schematic diagram of the adjustable delay module of the present invention.

FIG. 4 is a timing diagram of signals of a module under test.

Detailed Description

Explanation:

refclk reference clock.

CLK1_ o clock management unit CLK1 outputs.

CLK2_ o clock management unit CLK2 outputs.

fixed _ dly fixes the delay element.

The vari _ dly variable delay unit.

CLK1_ out is output with a fixed delay.

CLK2_ out goes through a variable delay output.

Compare _ out data comparator output.

The EN counter enables the signal.

The Count _ out counter outputs.

Referring to fig. 1, the digital circuit delay test circuit of the present invention includes the following parts:

and the counting module is used for counting the sending times of the test data between the starting moment and the moment when the control end receives the excitation signal. The counter is used as a statistical module in fig. 1.

The data generator is a random number generator (PRBS generator).

The invention integrates or uses programmable resources, a clock manager, a PRBS data generator, a data comparator, a delay unit (comprising a fixed delay unit and an adjustable delay unit), an M counter and related control signals in a chip.

The data comparator is used for carrying out logic XOR operation on the data output by the module to be tested and the data generated by the PRBS generator, when the data _ out is inconsistent with the data _ in data, a fail signal is output to the counter, the counter counts and outputs the TAP value of the current delay module, and the delay of the internal parameter can be known according to the TAP value.

The general structure of the invention is divided into 7 grades:

a first stage: a reference clock 101. It can be generated by an internal circuit of the chip or by an external clock of the chip.

And a second stage: a clock manager 102. The function of the clock is to output two paths of clocks which are the same as the frequency multiplication of the reference clock to the delay module.

And a third stage: and the clock is input to the delay module through the second stage. The delay of one clock is a fixed delay unit 103, and the delay of the other clock is an adjustable delay unit 104, which respectively provide a clock for the clock port of the unit to be tested and a clock for the data of the unit to be tested. A schematic diagram of the adjustable delay unit is shown in fig. 3. The invention combines the clock manager and the adjustable delay unit as an adjustable delay module, the output of which is shown in fig. 2. The fixed delay is a fixed value set by a register, and the variable delay is different delay values set by the register. In fig. 2, fixed _ dly refers to fixed delay, and Vari _ dly refers to variable delay (adjustable delay).

The time delay unit TAP is formed by cascading a plurality of time delay circuits, and the number of the TAP can be adjusted through setting a register. CLK1_ out is a fixed delay cell output waveform, CLK2_ out is a variable delay cell output waveform, and the period of each succeeding clock pulse of CLK2_ out is one TAP longer than the period of the preceding clock pulse. In practical applications, the number of TAPs and the delay time of the TAP unit are determined by each dut.

Fourth stage: and the M counter 105 is used for counting the number of the TAP (TAP list) of the delay unit and outputting the current number of the TAP when the fail signal is received when the EN receives the fail signal output by the seventh stage.

And a fifth stage: the timing diagram of the signal of the module under test 106 is shown in fig. 4.

A sixth stage: a PRBS generator 107, a pseudo random binary sequence (PRBS generator for short).

And a seventh stage: and the data comparator 108 is used for comparing the data of the sixth stage with the data output by the unit to be tested of the fifth stage, and outputting a fail signal to an EN port of the fourth-stage counter when the data are inconsistent.

When a chip to be tested generates a refclk reference clock by using internal logic (or a reference clock can be input through the outside of the chip), the clock manager starts to work and outputs CLK1_ o and CLK2_ o, the CLK1_ out and the CLK2_ out clocks are output after passing through the fixed/variable delay unit, the counter starts to count, then the CLK1_ out and the CLK2_ out are respectively provided for the unit to be tested, after the data to be tested is input into the module to be tested, the data _ out of the module to be tested is output to the data comparator to be compared with an expected value, and when the data comparator outputs a fail signal, the counter outputs the current count value.

Example (c): the frequency of the module to be tested is set to be 100MHz, the delay module comprises 64 TAP units, and the delay of each TAP is 50 ps.

The fixed delay unit is TAP1, the TAP value is set through the register in the delay of the adjustable delay module, when the fail signal is output by the data comparator, the EN signal of the counter is triggered, the current count value of the counter is 21, the delay of the unit to be tested is shown, when the data is output incorrectly in the variable delay unit TAP21, the delay time of the normal work of the module to be tested is 50 × 1 (21-1) ═ 1000ps ═ 1 ns.

Typical test results are shown in fig. 2.

Claims

1. The digital circuit delay testing circuit is characterized by comprising the following parts:

the clock manager is used for outputting a reference clock frequency multiplication signal to the fixed delay module and the adjustable delay module;

the fixed time delay unit is used for generating a fixed clock signal and outputting the fixed clock signal to a clock end of the module to be tested, wherein the fixed clock signal has a fixed time delay relative to a reference clock frequency multiplication signal;

the adjustable delay unit is used for generating a variable clock signal with adjacent cycle increment of t and outputting increment information to the statistical module;

and the counting module is used for counting the sending times of the test data between the starting moment and the moment when the control end receives the excitation signal, and providing a basis for calculating the delay time of the normal work of the module to be tested.

2. The digital circuit delay test circuit of claim 1, wherein the data generator is a random number generator.

3. The integrated circuit chip comprises a module to be tested and is characterized by also comprising a built-in digital circuit delay test circuit, wherein the digital circuit delay test circuit comprises the following parts: