CN1178009A - Delay time measuring method and pulse generator for measuring delay time for use in said measuring method - Google Patents
Delay time measuring method and pulse generator for measuring delay time for use in said measuring method Download PDFInfo
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- CN1178009A CN1178009A CN 97190033 CN97190033A CN1178009A CN 1178009 A CN1178009 A CN 1178009A CN 97190033 CN97190033 CN 97190033 CN 97190033 A CN97190033 A CN 97190033A CN 1178009 A CN1178009 A CN 1178009A
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Abstract
A method for accurately measuring the delay time of a signal path(10) constituted by an IC of a CMOS structure in a state which is the same as, or approximate to, the actual operation state. A loop oscillation circuit including the signal path (10) is constittuted, and is brought into a loop oscillation state by feeding a start pulse ST to the circuit. An interpolation pulse P1 having a frequency which is the same as, or approximate to, the frequency of the pulse signal propagated with the signal path is in an actual operation state, is inserted, this interpolation pulse P1 and the loop oscillation signal PLO are fed to the signal path, and the signal path is brought into the substantially same temperature state as that of the actual operation state. The cycle of the loop oscillation signal PLO is measured under this state so as to measure the delay time of the signal path.
Description
Assay method time delay when the present invention relates to a kind of time delay that is applicable to the signal that transmits in each signal path that is determined in the device with a plurality of signal paths relates in particular to a kind of time delay of assay method and for implementing the pulse generator for measuring delay time for use in said that this method is used that makes each signal path be in the delay reality of measuring this signal path with the identical state of actual working state or the state close with it.
In the IC test unit of for example various SIC (semiconductor integrated circuit) (hereinafter referred to as IC) being tested (being called the IC tester), the test signal that adds prescribed model to each input terminal of the IC of reception test (by testing IC), and with the expectation value signal relatively with its response output signal, when two signals are inconsistent, produce bad (FAIL) signal, judge based on the bad signal that produces whether by test IC be substandard products.Therefore, on the IC test unit, be provided with at least with by the feed path of the same number of test signal of the input terminal of test IC, i.e. signal path.The IC test unit have can implement simultaneously to 16,32,64 etc. a plurality of by the structures of the test of test IC, can test a large amount of IC at short notice.So, in fact in the IC test unit, be provided with the signal path of hundreds of passages.
But, offer by the phase place of the test signal of the pattern of the regulation of each input terminal of test IC, need be adjusted into desired phase place according to test objective.For this reason, must provide with given value the time delay in the signal path of each test signal.And requiring preferably, the signal path of all test signals has consistent time delay (being identical).Therefore, and compare in the past, carrying out termly in IC test unit field eliminating the error of time delay and becoming the adjustment operation of same delay time to the mensuration of time delay of each test signal feed path and based on measurement result.
Be not limited only to the IC test unit, in the circuit that has by each path of a plurality of signal paths backward level or element (parts) electronic installation or integrated circuit by the structure of the signal (pulse) of for example clock signal etc., or in test unit or various determinator that other electronic unit outside the IC that has a plurality of signal paths equally or element are tested, also need to be determined at the time delay of the signal that transmits in each signal path, and eliminate the error of time delay and become the adjustment operation of same delay time, or make signal offer the operation of adjustment time delay of the circuit of back level or element with the phase place of regulation based on measurement result.
So, eliminate each signal path time delay error and be adjusted into the operation of same delay time or adjust time delay so that phase place in accordance with regulations provides the operation of signal, be commonly referred to as skew adjustment.
An embodiment of existing time delay of assay method is described with reference to Fig. 3.Fig. 3 represents and will 20 be connected a circuit structure on the signal path 10 for determinator time delay of implementing that this time delay, assay method used.Usually, each signal path 10 is to be made of the signal path 11 of a plurality of logic elements of series connection and the variable delay device 12 that is inserted in the described signal one tunnel.Variable delay device 12 is for being provided with the time delay of adjusting signal path 10.In various determinators, described signal path 10 for example can be regarded as from the timing signal generating unit provides a plurality of signal paths of clock signal (timing signal) one to determined device.And, in the IC test unit, can regard as from mode generator to a plurality of signal paths of test signal that prescribed model is provided by test IC.
For time delay in measured signal path 10 with time delay determinator 20 be connected to the input end 14 of signal path 10.The output terminal 13 of signal path 10 is connected on the determinator 20 time delay by connecting path 21, forms following loop: the input end 14 of signal path 10 → its output terminal 13 → connecting path determinator 21 → time delay 20 → signal path 10.Time delay, determinator 20 was by provide oscillation circuit to constitute with the beginning pulse producer 22 that begins pulse ST and the counter 23 in the cycle of measuring the pulse that transmits in described loop to signal path 10.
The following describes assay method time delay.As if beginning pulse ST from beginning pulse producer 22 to one of input end 14 input of signal path 10, then after second, described beginning pulse ST is exported to output terminal 13 to process by the delay time T of signal path 10 generations.Can ignore if compare the time delay of connecting path 21 comparatively fully little with the time delay of signal path 10, then τ is after second, and the pulse meeting that transmits at signal path 10 is fed to input end 14.The pulse that is fed exports the output terminal 13 of signal path 10 again to after second through τ, feed back to input end 14 again.As shown in Figure 4, the loop that comprises signal path 10 is by so repeatedly, and the cycle of becoming is the oscillation circuit state of the delay time T that has of signal path 10.Counter 23 is measured oscillation circuit signal P
LOCycle and obtain the delay time T of signal path 10.
In described existing time delay assay method, if the delay time T of signal path 10 is short and oscillation circuit signal P
LOThe frequency of frequency when being similar to the real work (hereinafter referred to as positive activity) of signal path 10, the most close time delay of time delay of signal path in the time of then can measuring with positive activity.But,, therefore in the circuit of various determinators, test unit etc., tend to use the IC of IC (MOSIC), especially CMOS (the phase apotype MOS) structure of MOS structure owing to tend to require miniaturization and low consumpting powerization recently.Because the IC consumed power of CMOS structure is very little and can realize high integration, therefore has the advantage that can realize miniaturization.
But, because the consumption path that is made of the IC of CMOS structure or the propagation delay time of the signal in the circuit are long, therefore when constituting aforesaid signal path 10 by the IC of CMOS structure, if utilize described existing time delay assay method to make the loop that comprises this signal path 10 carry out oscillation circuit for measuring delay time T, then its oscillation circuit frequency is lower frequency.
Giving one example, is when IC by the CMOS structure constitutes, to be about 100ns its time delay from the waveform generation of the test signal of prescribed model to its test signal being offered by the circuit of the terminal of test IC in the IC test unit.If be 100ns time delay, then the oscillation circuit frequency is 1/100ns=10MHz.On the other hand, in the IC test unit with the frequency setting of test signal high-frequency for about 100MHz.Therefore, produce than big difference between the frequency number when the frequency of oscillation circuit and positive activity.
In various determinators or electronic installation, when for example using high-frequency markers (clock) signal, if constitute the signal path that is provided described timing signal, then between the frequency of the frequency of oscillation circuit and positive activity, also produce than big difference by the IC of CMOS structure.
Another shortcoming of the IC of CMOS structure is, owing to have the only characteristic of ability consumed power when the state counter-rotating of active component, so consumed power changes with operating rate.For example, signal path 10 to working when positive activity with 100MHz, by 1/10 of its frequency is that 10MHz carries out oscillation circuit and when measuring its time delay, because the consumed power when 100MHz and 10MHz has difference, so the IC temperature inside is a temperature different during with positive activity.Because the delay time T of the IC of CMOS structure changes with the IC temperature inside, therefore, the shortcoming of the time delay accurately when generation can not be measured positive activity.
First purpose of the present invention is to provide a kind of assay method time delay that can measure the time delay identical in fact with the time delay of the signal path that is in the positive activity state.
It is a kind of for implementing the described pulse generator for measuring delay time for use in said that time delay of the present invention, assay method used that second purpose of the present invention is to provide.
For realizing first above-mentioned purpose, according to assay method time delay of the present invention, constitute the oscillation circuit circuit that comprises the signal path that to measure time delay, in the cycle of the oscillator signal of described oscillation circuit circuit, insert and be under the positive activity state at described signal path, the frequency of the signal that in described signal path, transmits equate or with the signal of its close frequencies, and described oscillator signal transmitted in described signal path with signal in the cycle that is inserted in described oscillator signal and make described signal path be in identical with the positive activity state in fact state, take out the oscillator signal of described oscillation circuit circuit and measure its cycle, with time delay in described cycle of recording as described signal path.
In most preferred embodiment, described signal path is that the IC by the CMOS structure constitutes, and inserts in the cycle of described oscillation circuit signal and be in the insertion pulse that equates on the frequency configuration of the signal that transmits under the positive activity state at described signal path in described signal path.
And, the quantity that is inserted in the insertion pulse in cycle of described oscillation circuit signal is set in advance in the storer, if rolling counters forward is Duoed one insertion pulse than the insertion pulse of the quantity of described setting, then described counter produces output signal, and time delay of measuring described signal path in the cycle of the output signal by described counter.
For realizing the second above-mentioned purpose, comprise for implementing the pulse generator for measuring delay time for use in said that described time delay, assay method used according to of the present invention: the beginning pulse producer, generation is used to make the oscillation circuit circuit that comprises the signal path that should measure time delay to carry out the beginning pulse of oscillation circuit; The synchronized oscillation circuit, be synchronized with the oscillation circuit signal of described oscillation circuit circuit and vibrate, and make and equate with the frequency that is in the pulse signal that under the positive activity state, in described signal path, transmits at described signal path or in the cycle of described oscillation circuit signal, vibrate with the pulse signal of its close frequencies; Storer, the quantity of storing the pulse signal that described synchronized oscillation circuit vibrates in the cycle of described oscillation circuit signal; Counter, the quantity of the pulse signal that described synchronized oscillation circuit was vibrated in the cycle of described oscillation circuit signal is counted; Gate circuit, described counter if count a pulse signal again, then stop the vibration of described synchronized oscillation circuit after the quantity of the pulse signal that only vibrates with the numerical value that is stored in the described storer is counted in the cycle of described oscillation circuit signal; The pulse extractor from the train of impulses that the described oscillation circuit signal of the feedback by transmitting and the described pulse signal that vibrates are formed, only takes out described oscillation circuit signal in the cycle of described oscillation circuit signal described signal path; Controller makes described counter turn back to original state by the described oscillation circuit signal that takes out by described pulse extractor, and restarts the vibration of described synchronized oscillation circuit.
Time delay according to the present invention assay method, the signal path that should measure time delay is in the state identical in fact with the positive activity state, the time delay in measured signal path under the duty identical with described positive activity state.Therefore, can obtain the time delay accurately that equates in fact time delay with under the positive activity state of signal path.
And,, can make signal path be in the state identical by better simply circuit with the positive activity state according to pulse generator for measuring delay time for use in said of the present invention.Therefore, easily realize according to assay method time delay of the present invention.
Brief description of drawings:
Fig. 1 is expressed as to implement assay method and the block diagram of the circuit structure of the pulse generator for measuring delay time for use in said that uses time delay of the present invention;
Fig. 2 is the sequential chart that is used to illustrate the work of pulse generator for measuring delay time for use in said shown in Figure 1;
Fig. 3 be expressed as implement existing time delay assay method and use time delay the determinator circuit structure block diagram;
Fig. 4 is the sequential chart that is used to illustrate the work of shown in Figure 3 time delay of determinator.
Below, the detailed description embodiments of the invention see figures.1.and.2.
Fig. 1 is expressed as and implements assay method and the pulse generator for measuring delay time for use in said 30 that uses is connected a circuit structure on the signal path 10 time delay of the present invention.In this embodiment, also with signal path 10 shown in Figure 3 in the same manner, each signal path 10 is made of the signal path of a plurality of logic elements of series connection and the variable delay device that is inserted in this signal path.And, in various mensuration circuit, each signal path 10 for example can be regarded as from the timing signal generating unit provides a plurality of signal paths of timing signal (timing signal) one to determined device, and, in the IC test unit, can regard as from mode generator to a plurality of signal paths of test signal that prescribed model is provided by test IC.
For implementing according to assay method time delay of the present invention, pulse generator for measuring delay time for use in said 30 is connected to the input end 14 of signal path 10, and the frequency of the signal that transmits when signal path 10 provides with real action is identical or with the pulse of its close frequencies.
Because the output terminal 13 of signal path 10 is to be connected on the pulse generator for measuring delay time for use in said 30 by connecting path 21, therefore form following loop: the input end 14 of signal path 10 → its output terminal 13 → connecting path 21 → pulse generator for measuring delay time for use in said 20 → signal path 10.
Pulse generator for measuring delay time for use in said 30 comprises: beginning pulse producer 35 produces oscillation circuit with beginning pulse ST; Counter 41 is imported the oscillation circuit signal P that feeds back by connecting path to it
LOController 42 is controlled described counter 41; AND circuit 31 will be by the oscillation circuit signal P of connecting path 21 feedbacks
LOOffer non-counter-rotating input end, the output of counter 41 is offered the counter-rotating input end; Storer 38, storage can be inserted in the insertion pulse P in the oscillation circuit cycle
INumber; Synchronized oscillation circuit 36 provides the output of AND circuit 31 and the output of beginning pulse producer 35 to it; Counter 39 provides the output of described synchronized oscillation circuit 36 to it; Controller 40 is used for presetting the insertion pulse P that is stored in storer 38 to described counter
INumerical value.
Synchronized oscillation circuit 36 comprises: OR circuit 32 provides the output of AND circuit 31, the output of beginning pulse producer 35 and the output of synchronized oscillation circuit 36 to it; Pulse shaping circuit 33 carries out wave shaping to the output of described OR circuit 32; AND circuit 34 is imported the output of the output sum counter 39 of described pulse shaping circuit 33 to it.The output of AND circuit 34 is provided for the input end 14 of signal path 10.Thus, AND circuit 31 and synchronized oscillation circuit 36 constitute the part of backfeed loop, thereby signal path 10, connecting path 21, AND circuit 31 and synchronized oscillation circuit 36 (OR circuit 32, pulse shaping circuit 33 and AND circuit 34) constitute the oscillation circuit circuit.
Therefore,, then begin to carry out oscillation circuit, shown in the A among Fig. 2, become oscillation circuit signal P if provide beginning pulse ST to synchronized oscillation circuit 36 from beginning pulse producer 35
LOWith the oscillation circuit state that in described loop, transmits repeatedly by the cycle of the delay time T of signal path 10 decision.
In time delay according to the present invention assay method, shown in the B among Fig. 2, at oscillation circuit signal P
LOPeriod tau in (at two adjacent oscillation circuit signal P
LOBetween) insertion pulse P
IDescribed insertion pulse P
IFrequency be chosen to be, equate or the frequency close with the frequency of the signal that transmits in working order a certain signal path 10 with it.Therefore, insert pulse P
IFrequency perhaps the difference because of device is different, but it is known value.
Equate with the frequency of the signal that in the signal path 10 of positive activity state, transmits or the insertion pulse P of the frequency close if will have with it
IBe inserted into oscillation circuit signal P
LOPeriod tau in, then described insertion pulse P
IWith oscillation circuit signal P
LOIn signal path 10, transmit together.Therefore, signal path 10 is in the state identical or close with it with the positive activity state.Its result, the power that the power that consumes in signal path 10 consumes during in fact with positive activity is identical, so the temperature variation of signal path 10 is identical during in fact also with positive activity.So, according to assay method time delay of the present invention, can be under the temperature change state identical in fact with the temperature change of the signal path 10 of positive activity state, the time delay in measured signal path 10, therefore, even if signal path 10 constitutes the correct time delay that the time delay of the signal path 10 in the time of also can measuring with positive activity is identical in fact by the IC of CMOS structure.
What described synchronized oscillation circuit 36 was represented is the situation that is made of the synchronized oscillation circuit the loop, and described loop is directly fed back to feedback network 37, OR circuit 32, pulse shaping circuit 33 and the AND circuit 34 of OR circuit 32 by the pulse that will obtain from the output of AND circuit 34.Thereby, by comprising the short loop of feedback network 37, produce and equate with the frequency of the signal of transmission in the signal path 10 of positive activity state or the insertion pulse P of the frequency close with it
IAnd the wave shaping of the pulse that pulse shaping circuit 33 will be transfused to is the pulse of regulation amplitude, carries out the peak value of this pulse is enlarged into the work of setting simultaneously.Keep oscillation circuit work by this amplitude amplification work.
Storage is inserted into the insertion pulse P of oscillation period in the τ of the oscillation circuit circuit that comprises signal path 10 in the storer 38 of described pulse generator for measuring delay time for use in said 30
IQuantity.Though τ oscillation period of oscillation circuit circuit is tried to achieve by measurement, carrying on a shoulder pole this measured value also can be big probable value.If be inserted into the insertion pulse P in τ oscillation period
IQuantity be N, then set numerical value of N to storer 38.Described numerical value of N primitively is preset in the counter 39 by beginning pulse ST under the control of controller 40.39 couples of insertion pulse P of counter as the vibration output of synchronized oscillation circuit 36
ICount, whenever pulse P is inserted in input
I, just from prevalue, subtract 1 (1).If the prevalue of counter 39 becomes 0 and at the insertion pulse P of counting
INumerical value coexist and count a pulse of back after the numerical value of N unanimity of setting in the storer, then the output of counter 39 drops to L (low level) logic.Its result become pass (OFF) state with door 34, so the oscillatory work of synchronized oscillation circuit 36 stops temporarily.
The oscillation circuit signal P that feeds back from signal path 10 process connecting paths 21
LO, be input to controller 40 through AND circuit 31, and be preset to once again in the counter 39 by the numerical value of N of control store in storer 38 of described controller 40.By presetting of this numerical value of N, the output of counter 39 returns to H (high level) logic, so AND circuit 34 becomes out (ON) state (enable state), makes oscillation circuit signal P
LOBy.Thus, restart the oscillatory work of synchronized oscillation circuit 36.AND circuit 31 is carried out from only taking out oscillation circuit signal P through connecting path 21 train of impulses of feedback with counter and controller 42 cooperations
LOWork.That is, carry out from by an oscillation circuit signal P
LOWith the insertion pulse P that is connected on after this
ITake out the work of first pulse in the train of impulses that string is formed.With counter 39 in the same manner, counter 41 under the control of controller 38, by the beginning pulse ST and and oscillator signal P
LONumerical value preset to the numerical value of N that is stored in the storer 38.If counter 41 is preset the numerical value in the storer 38, counter 41 becomes the H logic, therefore is provided for an input terminal of AND circuit 31 as the L logic of its counter-rotating output.Thus, AND circuit 31 is in off status, stops to be connected on oscillation circuit signal P
LOPassing through of the train of impulses of back.
The insertion pulse P of feedback whenever being transfused to process connecting path 21
IThe time, counter 41 subtracts 1 (1) from prevalue N.If become the next pulse P that inserts of 0 back counting at described prevalue N
I, then the output of counter 41 drops to the L logic, so AND circuit 31 is in out state.Thus, the oscillation circuit signal P of feedback
LOThrough being input to controller 40 and 42 with door 31, counter 39 and 41 is preset thus.Turn back to out state by described presetting with door 31, the result makes oscillation circuit signal P with 31 at door
LOBy.So, the period tau (C among Fig. 2) of the output signal by instrumentation counter 39 or 41, but the time delay in measured signal path 10.Owing in signal path 10, transmitting oscillation circuit signal P
LOWith insertion pulse P
I, identical state when signal path 10 becomes in fact with positive activity thus, thereby the oscillation circuit signal P shown in the C among Fig. 2
LOTime delay of the signal path 10 of period tau during in fact with positive activity identical.That is time delay accurately that, can measured signal path 10.
And, in described pulse generator for measuring delay time for use in said,, counter 41 and controller 42 are set in addition with control and door 31 by counter 39 and controller 40 controls and door 34, but also counter 41 and controller 42 can be set in addition, and dual-purpose counter 39 and controller 40.And, be with synchronized oscillation circuit 36 as the oscillation circuit circuit, but unquestionable, also can use the synclator of other form or structure.
As mentioned above, according to the present invention, even it is long and comprise under the lower situation of the oscillation frequency of oscillation circuit circuit of described signal path in propagation delay time of signal path, also the frequency of the signal that can transmit with the positive activity of its signal path the time equate or with the insertion pulse of its close frequencies, be inserted in the oscillation circuit cycle and the time delay in measured signal path, therefore signal path about equally consumed power work with positive activity the time, temperature variation in fact also equates.Its result, the bigger signal path even be acted upon by temperature changes the time delay when constituting signal path as the IC by the CMOS structure, the time delay of the signal path (IC chip) in the time of also can measuring with positive activity under the roughly the same state of temperature, therefore, has the remarkable advantage that to measure free from error time delay accurately.
Claims (6)
- One kind time delay assay method, constitute the oscillation circuit circuit that comprises the signal path that to measure time delay, and the cycle of the oscillator signal by measuring described oscillation circuit circuit measure the time delay of described signal path, it is characterized in that, described time delay assay method, in the cycle of the oscillator signal of described oscillation circuit circuit, insert and be under the positive activity state at described signal path, the frequency of the signal that in described signal path, transmits equate or with the signal of its close frequencies, and described oscillator signal transmitted in described signal path with signal in the cycle that is inserted in described oscillator signal and make described signal path be in identical with the positive activity state in fact state, take out the oscillator signal of described oscillation circuit circuit and measure its cycle, with time delay in described cycle of recording as described signal path.
- 2. time delay as claimed in claim 1, assay method is characterized in that, described signal path is that the IC by the CMOS structure constitutes.
- 3. time delay as claimed in claim 1 assay method, it is characterized in that, the interior signal of cycle that is inserted in described oscillator signal is a pulse signal, the quantity of the described pulse signal that inserts is set in advance in the storer, when counting down to when Duoing one pulse signal, measure from time delay in cycle of the signal of counter output as described signal path than the pulse signal of the quantity of described setting.
- 4. time delay as claimed in claim 1, assay method is characterized in that, in various determinators, described signal path is to provide a plurality of signal paths of timing signal one from the timing signal generating unit to determined chip.
- 5. time delay as claimed in claim 1, assay method is characterized in that, in the IC test unit, described signal path is from mode generator to a plurality of signal paths of the test signal that supplied a pattern by test IC.
- 6. pulse generator for measuring delay time for use in said, it is characterized in that, described pulse generator for measuring delay time for use in said is to use for implementing assay method time delay described in each of claim 1 to 5, comprise: the beginning pulse producer, generation is used to make the oscillation circuit circuit that comprises the signal path that should measure time delay to carry out the beginning pulse of oscillation circuit; The synchronized oscillation circuit, be synchronized with the oscillation circuit signal of described oscillation circuit circuit and vibrate, and make and equate with the frequency that is in the pulse signal that under the positive activity state, in described signal path, transmits at described signal path or in the cycle of described oscillation circuit signal, vibrate with the pulse signal of its close frequencies; Storer, the quantity of storing the pulse signal that described synchronized oscillation circuit vibrates in the cycle of described oscillation circuit signal; Counter, the quantity of the pulse signal that described synchronized oscillation circuit was vibrated in the cycle of described oscillation circuit signal is counted; Gate circuit, described counter if count a pulse signal again, then stop the vibration of described synchronized oscillation circuit after the quantity of the pulse signal that only vibrates with the numerical value that is stored in the described storer is counted in the cycle of described oscillation circuit signal; The pulse extractor from the train of impulses that the described oscillation circuit signal of the feedback by transmitting and the described pulse signal that vibrates are formed, only takes out described oscillation circuit signal in the cycle of described oscillation circuit signal described signal path; Controller makes described counter turn back to original state by the described oscillation circuit signal that takes out by described pulse extractor, and restarts the vibration of described synchronized oscillation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 97190033 CN1178009A (en) | 1996-01-25 | 1997-01-24 | Delay time measuring method and pulse generator for measuring delay time for use in said measuring method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10920/96 | 1996-01-25 | ||
| CN 97190033 CN1178009A (en) | 1996-01-25 | 1997-01-24 | Delay time measuring method and pulse generator for measuring delay time for use in said measuring method |
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| CN1178009A true CN1178009A (en) | 1998-04-01 |
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| CN 97190033 Pending CN1178009A (en) | 1996-01-25 | 1997-01-24 | Delay time measuring method and pulse generator for measuring delay time for use in said measuring method |
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| CN100353172C (en) * | 2002-09-17 | 2007-12-05 | 联发科技股份有限公司 | Group delay test method and device thereof |
| CN100430745C (en) * | 2005-08-08 | 2008-11-05 | 联华电子股份有限公司 | Delay time measuring device and method |
| CN101995530A (en) * | 2010-11-18 | 2011-03-30 | 四川九洲电器集团有限责任公司 | Closed-loop adaptive ranging working method |
| CN102257725A (en) * | 2008-12-18 | 2011-11-23 | 松下电器产业株式会社 | Oscillation circuit |
| CN101680920B (en) * | 2007-06-18 | 2012-02-08 | 艾勒博科技股份有限公司 | delay time measurement circuit and method |
| CN102654572A (en) * | 2011-03-03 | 2012-09-05 | 河北省电力研究院 | Testing method for delayed output time of signal control terminal of intelligent electric energy meter |
| CN103163449A (en) * | 2013-04-01 | 2013-06-19 | 河海大学常州校区 | Time delay detection system for signal circuit |
| CN104579171A (en) * | 2013-10-16 | 2015-04-29 | 精工爱普生株式会社 | Oscillation circuit, oscillator, electronic device, and moving object |
| CN105699734A (en) * | 2014-11-26 | 2016-06-22 | 环旭电子股份有限公司 | Device and method for detecting delay time of signal |
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- 1997-01-24 CN CN 97190033 patent/CN1178009A/en active Pending
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| CN100353172C (en) * | 2002-09-17 | 2007-12-05 | 联发科技股份有限公司 | Group delay test method and device thereof |
| CN100430745C (en) * | 2005-08-08 | 2008-11-05 | 联华电子股份有限公司 | Delay time measuring device and method |
| CN101680920B (en) * | 2007-06-18 | 2012-02-08 | 艾勒博科技股份有限公司 | delay time measurement circuit and method |
| CN102257725B (en) * | 2008-12-18 | 2014-05-21 | 松下电器产业株式会社 | Oscillation circuit |
| CN102257725A (en) * | 2008-12-18 | 2011-11-23 | 松下电器产业株式会社 | Oscillation circuit |
| CN101995530B (en) * | 2010-11-18 | 2013-01-23 | 四川九洲电器集团有限责任公司 | Closed-loop adaptive ranging working method |
| CN101995530A (en) * | 2010-11-18 | 2011-03-30 | 四川九洲电器集团有限责任公司 | Closed-loop adaptive ranging working method |
| CN102654572A (en) * | 2011-03-03 | 2012-09-05 | 河北省电力研究院 | Testing method for delayed output time of signal control terminal of intelligent electric energy meter |
| CN102654572B (en) * | 2011-03-03 | 2014-08-13 | 河北省电力公司电力科学研究院 | Testing method for delayed output time of signal control terminal of intelligent electric energy meter |
| CN103163449B (en) * | 2013-04-01 | 2016-04-06 | 河海大学常州校区 | Signal circuit time delay detection system |
| CN103163449A (en) * | 2013-04-01 | 2013-06-19 | 河海大学常州校区 | Time delay detection system for signal circuit |
| CN104579171A (en) * | 2013-10-16 | 2015-04-29 | 精工爱普生株式会社 | Oscillation circuit, oscillator, electronic device, and moving object |
| CN105699734A (en) * | 2014-11-26 | 2016-06-22 | 环旭电子股份有限公司 | Device and method for detecting delay time of signal |
| CN114545192A (en) * | 2020-11-27 | 2022-05-27 | 上海寒武纪信息科技有限公司 | Test circuit for quantizing static delay time sequence |
| CN114545192B (en) * | 2020-11-27 | 2024-01-26 | 上海寒武纪信息科技有限公司 | Test circuit for quantifying static delay time sequence |
| CN112816858A (en) * | 2020-12-31 | 2021-05-18 | 成都华微电子科技有限公司 | Digital circuit delay test method, test circuit and integrated circuit chip |
| CN112816858B (en) * | 2020-12-31 | 2022-09-16 | 成都华微电子科技股份有限公司 | Digital circuit delay test method, test circuit and integrated circuit chip |
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