CN112816858A - Digital circuit delay test method, test circuit and integrated circuit chip - Google Patents
Digital circuit delay test method, test circuit and integrated circuit chip Download PDFInfo
- Publication number
- CN112816858A CN112816858A CN202011636594.7A CN202011636594A CN112816858A CN 112816858 A CN112816858 A CN 112816858A CN 202011636594 A CN202011636594 A CN 202011636594A CN 112816858 A CN112816858 A CN 112816858A
- Authority
- CN
- China
- Prior art keywords
- module
- data
- delay
- test
- tested
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 47
- 238000010998 test method Methods 0.000 title abstract description 3
- 230000005284 excitation Effects 0.000 claims abstract description 14
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 101150071746 Pbsn gene Proteins 0.000 description 5
- 102100035174 SEC14-like protein 2 Human genes 0.000 description 4
- 238000005259 measurement Methods 0.000 description 3
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 1
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 1
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 1
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 1
- 108010023335 Member 2 Subfamily B ATP Binding Cassette Transporter Proteins 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31702—Testing digital circuits including elements other than semiconductor transistors, e.g. biochips, nanofabrics, mems, chips with magnetic elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
A digital circuit delay test method, a test circuit and an integrated circuit chip relate to the integrated circuit technology. The digital circuit delay testing method comprises the following steps: 1) sending test data to a data port of a module to be tested at an initial moment, wherein the time increment between two adjacent test data is t; 2) comparing the output data and the input data of the module to be tested, and outputting an excitation signal when the output data and the input data are inconsistent; 3) and counting the sending times of the test data between the starting moment and the sending moment of the excitation signal, and calculating the time delay of the module to be tested by combining the t value. The invention reduces the influence of chip packaging, input and output circuits, PCB wiring and the like on the testing delay precision.
Description
Technical Field
The present invention relates to integrated circuit technology.
Background
In the prior art, the measurement of the digital circuit delay is based on an external measurement circuit, the precision is restricted by the external circuit, and the requirement of on-site real-time measurement cannot be met.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a digital circuit delay testing technology built in a chip, which can accurately test the delay performance of a functional module.
The technical scheme adopted by the invention for solving the technical problems is that the digital circuit delay testing method is characterized by comprising the following steps:
1) sending test data to a data port of a module to be tested at an initial moment, wherein the time increment of two adjacent intervals is t, and the interval is the time between two adjacent test data;
2) comparing the output data and the input data of the module to be tested, and outputting an excitation signal when the output data and the input data are inconsistent;
3) and counting the sending times of the test data between the starting moment and the sending moment of the excitation signal, and calculating the time delay of the module to be tested by combining the t value.
The invention also provides a digital circuit delay test circuit, which comprises the following parts:
the adjustable delay module is used for generating a variable clock signal with adjacent cycle increment of t and outputting increment information to the statistical module;
the test data generator is connected with the adjustable delay module and used for sending test data to the module to be tested when receiving the output signal excitation edge of the adjustable delay module;
the first input end of the data comparator is connected with the data output end of the module to be tested, the second input end of the data comparator is connected with the output end of the test data generator, and the output end of the data comparator is connected with the control end of the statistical module;
and the counting module is used for counting the sending times of the test data between the starting moment and the moment when the control end receives the excitation signal.
The data generator is a random number generator.
The invention also provides an integrated circuit chip with the built-in digital circuit delay test circuit.
The invention can accurately test the time delay of the internal functional module of the chip, reduces the dependence on external instruments by adopting a built-in mode, and reduces the influence of chip packaging, input and output circuits, PCB routing and the like on the test time delay precision.
Drawings
FIG. 1 is a schematic diagram of a test circuit according to the present invention.
Fig. 2 is a timing diagram of the present invention.
Fig. 3 is a schematic diagram of the adjustable delay module of the present invention.
FIG. 4 is a timing diagram of signals of a module under test.
Detailed Description
Explanation:
refclk reference clock.
CLK1_ o clock management unit CLK1 outputs.
CLK2_ o clock management unit CLK2 outputs.
fixed _ dly fixes the delay element.
The vari _ dly variable delay unit.
CLK1_ out is output with a fixed delay.
CLK2_ out goes through a variable delay output.
Compare _ out data comparator output.
The EN counter enables the signal.
The Count _ out counter outputs.
Referring to fig. 1, the digital circuit delay test circuit of the present invention includes the following parts:
the adjustable delay module is used for generating a variable clock signal with adjacent cycle increment of t and outputting increment information to the statistical module;
the test data generator is connected with the adjustable delay module and used for sending test data to the module to be tested when receiving the output signal excitation edge of the adjustable delay module;
the first input end of the data comparator is connected with the data output end of the module to be tested, the second input end of the data comparator is connected with the output end of the test data generator, and the output end of the data comparator is connected with the control end of the statistical module;
and the counting module is used for counting the sending times of the test data between the starting moment and the moment when the control end receives the excitation signal. The counter is used as a statistical module in fig. 1.
The data generator is a random number generator (PRBS generator).
The invention integrates or uses programmable resources, a clock manager, a PRBS data generator, a data comparator, a delay unit (comprising a fixed delay unit and an adjustable delay unit), an M counter and related control signals in a chip.
The data comparator is used for carrying out logic XOR operation on the data output by the module to be tested and the data generated by the PRBS generator, when the data _ out is inconsistent with the data _ in data, a fail signal is output to the counter, the counter counts and outputs the TAP value of the current delay module, and the delay of the internal parameter can be known according to the TAP value.
The general structure of the invention is divided into 7 grades:
a first stage: a reference clock 101. It can be generated by an internal circuit of the chip or by an external clock of the chip.
And a second stage: a clock manager 102. The function of the clock is to output two paths of clocks which are the same as the frequency multiplication of the reference clock to the delay module.
And a third stage: and the clock is input to the delay module through the second stage. The delay of one clock is a fixed delay unit 103, and the delay of the other clock is an adjustable delay unit 104, which respectively provide a clock for the clock port of the unit to be tested and a clock for the data of the unit to be tested. A schematic diagram of the adjustable delay unit is shown in fig. 3. The invention combines the clock manager and the adjustable delay unit as an adjustable delay module, the output of which is shown in fig. 2. The fixed delay is a fixed value set by a register, and the variable delay is different delay values set by the register. In fig. 2, fixed _ dly refers to fixed delay, and Vari _ dly refers to variable delay (adjustable delay).
The time delay unit TAP is formed by cascading a plurality of time delay circuits, and the number of the TAP can be adjusted through setting a register. CLK1_ out is a fixed delay cell output waveform, CLK2_ out is a variable delay cell output waveform, and the period of each succeeding clock pulse of CLK2_ out is one TAP longer than the period of the preceding clock pulse. In practical applications, the number of TAPs and the delay time of the TAP unit are determined by each dut.
Fourth stage: and the M counter 105 is used for counting the number of the TAPs of the delay unit and outputting the current number of the TAPs when the EN receives the fail signal when the EN receives the seventh-stage output fail signal.
And a fifth stage: the timing diagram of the module under test 106 is shown in fig. 4.
A sixth stage: a PRBS generator 107, a pseudo random binary sequence (PRBS generator for short).
And a seventh stage: and the data comparator 108 is used for comparing the data of the sixth stage with the data output by the unit to be tested of the fifth stage, and outputting a fail signal to an EN port of the fourth-stage counter when the data are inconsistent.
When a chip to be tested generates a refclk reference clock by using internal logic (or a reference clock can be input through the outside of the chip), the clock manager starts to work and outputs CLK1_ o and CLK2_ o, the CLK1_ out and the CLK2_ out clocks are output after passing through the fixed/variable delay unit, the counter starts to count, then the CLK1_ out and the CLK2_ out are respectively provided for the unit to be tested, after the data to be tested is input into the module to be tested, the data _ out of the module to be tested is output to the data comparator to be compared with an expected value, and when the data comparator outputs a fail signal, the counter outputs the current count value.
Example (c): the frequency of the module to be tested is set to be 100MHz, the delay module comprises 64 TAP units, and the delay of each TAP is 50 ps.
The fixed delay unit is TAP1, the TAP value is set through the register in the delay of the adjustable delay module, when the fail signal is output by the data comparator, the EN signal of the counter is triggered, the current count value of the counter is 21, the delay of the unit to be tested is shown, when the data is output incorrectly in the variable delay unit TAP21, the delay time of the normal work of the module to be tested is 50 × 1 (21-1) ═ 1000ps ═ 1 ns.
Typical test results are shown in fig. 2.
Claims (4)
1. The digital circuit delay testing method is characterized by comprising the following steps of:
1) sending test data to a data port of a module to be tested at an initial moment, wherein the time increment between two adjacent test data is t;
2) comparing the output data and the input data of the module to be tested, and outputting an excitation signal when the output data and the input data are inconsistent;
3) and counting the sending times of the test data between the starting moment and the sending moment of the excitation signal, and calculating the time delay of the module to be tested by combining the t value.
2. The digital circuit delay testing circuit is characterized by comprising the following parts:
the adjustable delay module is used for generating a variable clock signal with adjacent cycle increment of t and outputting increment information to the statistical module;
the test data generator is connected with the adjustable delay module and used for sending test data to the module to be tested when receiving the output signal excitation edge of the adjustable delay module;
the first input end of the data comparator is connected with the data output end of the module to be tested, the second input end of the data comparator is connected with the output end of the test data generator, and the output end of the data comparator is connected with the control end of the statistical module;
and the counting module is used for counting the sending times of the test data between the starting moment and the moment when the control end receives the excitation signal.
3. The digital circuit delay test circuit of claim 2, wherein the data generator is a random number generator.
4. The integrated circuit chip comprises a functional module and is characterized by also comprising a built-in digital circuit delay test circuit, wherein the digital circuit delay test circuit comprises the following parts:
the adjustable delay module is used for generating a variable clock signal with adjacent cycle increment of t and outputting increment information to the statistical module;
the test data generator is connected with the adjustable delay module and used for sending test data to the module to be tested when receiving the output signal excitation edge of the adjustable delay module;
the first input end of the data comparator is connected with the data output end of the module to be tested, the second input end of the data comparator is connected with the output end of the test data generator, and the output end of the data comparator is connected with the control end of the statistical module;
and the counting module is used for counting the sending times of the test data between the starting moment and the moment when the control end receives the excitation signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202011636594.7A CN112816858B (en) | 2020-12-31 | 2020-12-31 | Digital circuit delay test method, test circuit and integrated circuit chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202011636594.7A CN112816858B (en) | 2020-12-31 | 2020-12-31 | Digital circuit delay test method, test circuit and integrated circuit chip |
Publications (2)
Publication Number | Publication Date |
---|---|
CN112816858A true CN112816858A (en) | 2021-05-18 |
CN112816858B CN112816858B (en) | 2022-09-16 |
Family
ID=75857237
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202011636594.7A Active CN112816858B (en) | 2020-12-31 | 2020-12-31 | Digital circuit delay test method, test circuit and integrated circuit chip |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN112816858B (en) |
Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5412580A (en) * | 1991-07-03 | 1995-05-02 | Hughes Aircraft Company | Pseudo-random vector generated testable counter |
CN1178009A (en) * | 1996-01-25 | 1998-04-01 | 株式会社爱德万测试 | Delay time measuring method and pulse generator for measuring delay time for use in said measuring method |
JP2002368813A (en) * | 2001-06-05 | 2002-12-20 | Nec Commun Syst Ltd | Delay time distribution measurement device |
US20030093730A1 (en) * | 2001-11-13 | 2003-05-15 | Achintya Halder | Systems and methods for testing integrated circuits |
CN1892235A (en) * | 2005-07-05 | 2007-01-10 | 夏普株式会社 | Test circuit, delay circuit, clock generating circuit, and image sensor |
CN1902502A (en) * | 2003-12-27 | 2007-01-24 | 皇家飞利浦电子股份有限公司 | Delay fault test circuitry and related method |
CN101467384A (en) * | 2006-03-31 | 2009-06-24 | 安立股份有限公司 | Data signal generating apparatus |
CN101915875A (en) * | 2010-07-30 | 2010-12-15 | 西安电子科技大学 | Method for measuring phase difference of common-period signals based on delay unit dedicated for FPGA |
CN102466779A (en) * | 2010-11-16 | 2012-05-23 | 北京中电华大电子设计有限责任公司 | Built-in testing method for delay of trigger and circuit |
CN103163449A (en) * | 2013-04-01 | 2013-06-19 | 河海大学常州校区 | Time delay detection system for signal circuit |
CN105158591A (en) * | 2014-06-04 | 2015-12-16 | 领特贝特林共有限责任两合公司 | Probabilistic digital delay measurement device |
CN105842610A (en) * | 2016-03-31 | 2016-08-10 | 复旦大学 | FPGA circuit transmission delay rest system and method based on TDC |
CN108351381A (en) * | 2015-08-14 | 2018-07-31 | 诺韦尔达公司 | High precision time measurement device |
CN108535630A (en) * | 2018-04-02 | 2018-09-14 | 成都锐成芯微科技股份有限公司 | A kind of chip detecting method and chip testing modular |
CN108736438A (en) * | 2018-05-30 | 2018-11-02 | 浙江朗威微系统有限公司 | Built-in Self Test function leakage protection circuit and its detection method |
CN109217951A (en) * | 2018-09-07 | 2019-01-15 | 深圳市紫光同创电子有限公司 | A kind of transmission delay test method and device based on FPGA |
CN110520745A (en) * | 2017-04-20 | 2019-11-29 | 高通股份有限公司 | Use the critical sensor circuit estimating timing relaxation of endpoint |
CN111983423A (en) * | 2020-07-28 | 2020-11-24 | 成都华微电子科技有限公司 | Chip routing time delay built-in detection circuit and detection method |
-
2020
- 2020-12-31 CN CN202011636594.7A patent/CN112816858B/en active Active
Patent Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5412580A (en) * | 1991-07-03 | 1995-05-02 | Hughes Aircraft Company | Pseudo-random vector generated testable counter |
CN1178009A (en) * | 1996-01-25 | 1998-04-01 | 株式会社爱德万测试 | Delay time measuring method and pulse generator for measuring delay time for use in said measuring method |
JP2002368813A (en) * | 2001-06-05 | 2002-12-20 | Nec Commun Syst Ltd | Delay time distribution measurement device |
US20030093730A1 (en) * | 2001-11-13 | 2003-05-15 | Achintya Halder | Systems and methods for testing integrated circuits |
CN1902502A (en) * | 2003-12-27 | 2007-01-24 | 皇家飞利浦电子股份有限公司 | Delay fault test circuitry and related method |
CN1892235A (en) * | 2005-07-05 | 2007-01-10 | 夏普株式会社 | Test circuit, delay circuit, clock generating circuit, and image sensor |
CN101467384A (en) * | 2006-03-31 | 2009-06-24 | 安立股份有限公司 | Data signal generating apparatus |
CN101915875A (en) * | 2010-07-30 | 2010-12-15 | 西安电子科技大学 | Method for measuring phase difference of common-period signals based on delay unit dedicated for FPGA |
CN102466779A (en) * | 2010-11-16 | 2012-05-23 | 北京中电华大电子设计有限责任公司 | Built-in testing method for delay of trigger and circuit |
CN103163449A (en) * | 2013-04-01 | 2013-06-19 | 河海大学常州校区 | Time delay detection system for signal circuit |
CN105158591A (en) * | 2014-06-04 | 2015-12-16 | 领特贝特林共有限责任两合公司 | Probabilistic digital delay measurement device |
CN108351381A (en) * | 2015-08-14 | 2018-07-31 | 诺韦尔达公司 | High precision time measurement device |
CN105842610A (en) * | 2016-03-31 | 2016-08-10 | 复旦大学 | FPGA circuit transmission delay rest system and method based on TDC |
CN110520745A (en) * | 2017-04-20 | 2019-11-29 | 高通股份有限公司 | Use the critical sensor circuit estimating timing relaxation of endpoint |
CN108535630A (en) * | 2018-04-02 | 2018-09-14 | 成都锐成芯微科技股份有限公司 | A kind of chip detecting method and chip testing modular |
CN108736438A (en) * | 2018-05-30 | 2018-11-02 | 浙江朗威微系统有限公司 | Built-in Self Test function leakage protection circuit and its detection method |
CN109217951A (en) * | 2018-09-07 | 2019-01-15 | 深圳市紫光同创电子有限公司 | A kind of transmission delay test method and device based on FPGA |
CN111983423A (en) * | 2020-07-28 | 2020-11-24 | 成都华微电子科技有限公司 | Chip routing time delay built-in detection circuit and detection method |
Non-Patent Citations (1)
Title |
---|
黄坤超: "时延测试方法研究", 《中国优秀硕士学位论文全文数据库 工程科技Ⅱ辑》 * |
Also Published As
Publication number | Publication date |
---|---|
CN112816858B (en) | 2022-09-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8736338B2 (en) | High precision single edge capture and delay measurement circuit | |
US7408371B2 (en) | Apparatus for measuring on-chip characteristics in semiconductor circuits and related methods | |
CN101019035B (en) | Precise time measurement apparatus and method | |
KR101184137B1 (en) | Clock transfer circuit and tester using the same | |
US6661266B1 (en) | All digital built-in self-test circuit for phase-locked loops | |
US6668346B1 (en) | Digital process monitor | |
JP3625400B2 (en) | Test circuit for variable delay element | |
CN111983423B (en) | Chip wiring delay built-in detection circuit and detection method | |
US6670800B2 (en) | Timing variation measurements | |
CN212622809U (en) | Detection circuit | |
US7945404B2 (en) | Clock jitter measurement circuit and integrated circuit having the same | |
CN115542131A (en) | Chip testing method and circuit | |
US7113886B2 (en) | Circuit and method for distributing events in an event stream | |
US9837170B2 (en) | Systems and methods for testing performance of memory modules | |
CN112816858B (en) | Digital circuit delay test method, test circuit and integrated circuit chip | |
EP1148340A2 (en) | All digital built-in self-test circuit for phase-locked loops | |
CN100529784C (en) | Testing device | |
US6879201B1 (en) | Glitchless pulse generator | |
CN115100998B (en) | Drive circuit, drive IC, drive equipment and display equipment | |
CN216595393U (en) | Time delay testing device | |
US11402431B2 (en) | Detection circuit and detection method | |
US7065684B1 (en) | Circuits and methods for measuring signal propagation delays on integrated circuits | |
US11482992B2 (en) | Clock sweeping system | |
US8793545B2 (en) | Apparatus and method for clock glitch detection during at-speed testing | |
US6759885B2 (en) | Self-calibrating clock generator for generating process and temperature independent clock signals |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Address after: No. 2201 and 2301, floor 22-23, building 1, No. 1800, middle section of Yizhou Avenue, high tech Zone, China (Sichuan) pilot Free Trade Zone, Chengdu, Sichuan 610041 Applicant after: Chengdu Hua Microelectronics Technology Co.,Ltd. Address before: 610000 22 / F, building 1, No. 1800, middle section of Yizhou Avenue, hi tech Zone, Chengdu City, Sichuan Province Applicant before: CHENGDU SINO MICROELECTRONICS TECHNOLOGY Co.,Ltd. |
|
GR01 | Patent grant | ||
GR01 | Patent grant |