CN109217951A - A kind of transmission delay test method and device based on FPGA - Google Patents
A kind of transmission delay test method and device based on FPGA Download PDFInfo
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- CN109217951A CN109217951A CN201811046288.0A CN201811046288A CN109217951A CN 109217951 A CN109217951 A CN 109217951A CN 201811046288 A CN201811046288 A CN 201811046288A CN 109217951 A CN109217951 A CN 109217951A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/30—Monitoring; Testing of propagation channels
- H04B17/309—Measuring or estimating channel quality parameters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
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Abstract
The present invention provides a kind of transmission delay test method and device based on FPGA, two clock phases constantly tightened are simulated by two periods different clock, and at the time of determining the efficient clock of two clocks along alignment by edge synchronization detection unit, and by signal receive determination unit determine fast clock acquisition less than slow clock signal at the time of, then the phase difference of two clocks is calculated along the number counted in time interval of the fast clock acquisition less than slow clock signal is aligned in two clock efficient clocks according to by counter, the transmission delay of circuit under test is determined in conjunction with the period of slow clock by the phase difference that is calculated again, effectively improve the accuracy of transmission delay test, user is enabled rationally to reduce design margin in FPGA application, the service performance of fpga chip can be given full play to.
Description
Technical field
The present invention relates to field of communication technology more particularly to a kind of transmission delay test methods and device based on FPGA.
Background technique
On-site programmable gate array FPGA (Field Programmable Gate Array) is a kind of semiconductor devices,
Inside includes the logic module of some repeatable programmings, mainly includes following three parts: configurable logic blocks CLB
(configurable logic block), input/output module IOB (input/outputblock) and programmable interconnected line
(programmable interconnect).FPGA is to carry out circuit design with hardware description language (such as Verilog), then
The bit stream file comprising all programmable logic module configuration information is generated by eda software, this bit stream is downloaded in FPGA
The configuration internal storage location in portion is completed to CLBs, and the configuration of IOBs and programmable interconnected line etc., is the technology of modern IC designs verifying
Mainstream.
Each programmed logical module inside FPGA, such as CLB, IOB and programmable interconnected line etc. can have one
The transmission delay of segment signal, and the delay of these modules can be with the manufacture craft of fpga chip, operating voltage, the change of temperature etc.
Change and change, is difficult to accurately calculate which results in the transmission delay of fpga chip internal signal.Eda software is by the design of user
It is converted into correct FPGA bit stream configuration information, it is necessary to meet the temporal constraint of user.Under normal conditions, manufacturer is to FPGA
Transmission delay measured and assessed, the maximum value of transmission delay is provided in product manual, user is according to this numerical value
It is developed to be designed, is all convergent to ensure timing of the FPGA under other running environment also.
Generally, manufacturer considers that extreme conditions to carry out the transmission time-delayed information of FPGA by the method for emulation
Coarse evaluation to guarantee that the FPGA produced can correctly be run, and emulates maximum transmitting time delay information and reality obtained
Border is compared to there is very big safe clearance, and which results in the performances that fpga chip can not play itself completely.In addition, if setting
Simulated conditions it is wrong, there is very big discrepancy in the delayed data that obtains in this way and actual capabilities, cause eda software analysis result and
Actual operation result is inconsistent.
Summary of the invention
The present invention provides a kind of transmission delay test method and device based on FPGA, to solve to be based in the prior art
Most severe condition emulates resulting maximum transmitting time delay information has biggish safe clearance, caused FPGA compared with practical
Chip is unable to give full play the technical issues of service performance.
In order to solve the above-mentioned technical problem, the invention adopts the following technical scheme:
The present invention provides the transmission delay test method of FPGA a kind of, the transmission delay test method of the FPGA includes:
It drives the first d type flip flop to carry out the alternating output of low level signal and high level signal by the first clock, and leads to
Cross the reception that second clock drives the second d type flip flop to carry out the signal that the first d type flip flop is exported；The period of first clock is
T1, the period of second clock are T2, and T1 is greater than T2；
Control counter is with the efficient clock of the first clock and second clock determined by edge synchronization detection unit along right
To count initial time at the time of neat, and the second d type flip flop determined by determination unit is received with signal and persistently receives the
To count end time at the time of when the signal terminating that one d type flip flop sends over, the signal of second clock output is counted
Number；
The phase difference and T1 of the first clock and second clock according to determined by the counting as counter, determine the first D
The transmission delay to be measured in the path to be measured between trigger and the second d type flip flop.
Further, the first clock, second clock, the first d type flip flop, the second d type flip flop, counter, Edge check list
Member and signal receive determination unit and are integrated in monolithic fpga chip.
Further, edge synchronization detection unit includes: third d type flip flop, four d flip-flop and the 5th d type flip flop,
Third d type flip flop and four d flip-flop are driven by the first clock and second clock respectively；
Control counter is with the efficient clock of the first clock and second clock determined by edge synchronization detection unit along right
To count initial time at the time of neat, and the second d type flip flop determined by determination unit is received with signal and persistently receives the
To count end time at the time of when the signal terminating that one d type flip flop sends over, the signal of second clock output is counted
Number includes:
It receives the signal of third d type flip flop and four d flip-flop output respectively by the 5th d type flip flop, and is touched in the 5th D
Device is sent out with the Forward on the efficient clock edge of second clock, signal controls the signal itself exported by height based on the received
When level signal is overturn to low level signal, determine efficient clock that current time is the first clock and second clock along alignment
Moment；
To count initial time at the time of control counter is aligned with the efficient clock of the first clock and second clock edge, with
And the second d type flip flop determined by determination unit is received with signal and persistently receives the signal end that the first d type flip flop sends over
To count end time at the time of when only, the signal of second clock output is counted.
Further, it includes: XOR gate and the 6th D touching for receiving the signal that XOR gate exports that signal, which receives determination unit,
Device is sent out, the 6th d type flip flop is driven by second clock；
Control counter is with the efficient clock of the first clock and second clock determined by edge synchronization detection unit along right
To count initial time at the time of neat, and the second d type flip flop determined by determination unit is received with signal and persistently receives the
To count end time at the time of when the signal terminating that one d type flip flop sends over, the signal of second clock output is counted
Number includes:
Control counter is with the efficient clock of the first clock and second clock determined by edge synchronization detection unit along right
Start to count the signal that second clock exports to count initial time at the time of neat；
The D port signal and Q port signal of the second d type flip flop are received from the second d type flip flop by XOR gate, and the 6th
When d type flip flop receives the high level signal of XOR gate output and triggered by second clock and export high level signal, determine
At the time of current time is when the second d type flip flop persistently receives the signal terminating that the first d type flip flop sends over；
When control counter persistently receives the signal terminating that the first d type flip flop sends over the second d type flip flop when
It carves to count end time, and the signal for stopping exporting second clock counts.
Further, control counter having with the first clock determined by edge synchronization detection unit and second clock
It is counting initial time at the time of clock is imitated along alignment, and the second d type flip flop determined by determination unit is received with signal and is held
It is to count end time at the time of when continued access receives the signal terminating that the first d type flip flop sends over, to second clock output
Signal count
What to be measured path both ends of the control counter respectively between the first d type flip flop and the second d type flip flop were accessed opens
In the case where turning off open and close conjunction, with the efficient clock edge of the first clock determined by edge synchronization detection unit and second clock
It is counting initial time at the time of alignment, and the second d type flip flop determined by determination unit is received with signal and is persistently received
To count end time at the time of when the signal terminating that the first d type flip flop sends over, the signal of second clock output is carried out
It counts, and obtains the first counting and second and count；
The phase difference and T1 of the first clock and second clock according to determined by the counting as counter, determine the first D
The transmission delay to be measured in the path to be measured between trigger and the second d type flip flop includes:
According to the first phase difference and T1 for counting identified first clock and second clock by first, the first D is determined
The first transmission delay between trigger and the second d type flip flop, and according to by second count determined by the first clock and the
The second phase difference and T1 of two clocks, determine the second transmission delay between the first d type flip flop and the second d type flip flop；
The difference of first transmission delay and the second transmission delay is determined as to the transmission delay to be measured in path to be measured.
The transmission delay test device based on FPGA that the present invention provides a kind of, comprising: the first clock, second clock,
One d type flip flop, the second d type flip flop, counter, edge synchronization detection unit and signal receive determination unit, the first d type flip flop
And second access path to be measured between d type flip flop；The port Q of first d type flip flop takes back the port D, the first clock by phase inverter
Period be T1, period of second clock is T2, and T1 is greater than T2；
The alternating output that first clock is used to that the first d type flip flop to be driven to carry out low level signal and high level signal；
The reception that second clock is used to that the second d type flip flop to be driven to carry out the signal that the first d type flip flop is exported；
At the time of edge synchronization detection unit is used to determine that the efficient clock edge of the first clock and second clock to be aligned；
Signal receives determination unit for determining that the second d type flip flop persistently receives the letter that the first d type flip flop sends over
Number terminate when at the time of；
Counter is used to be to count initial time, and receive with signal with the moment determined by edge synchronization detection unit
Moment determined by determination unit is to count end time, is counted to the signal of second clock output；The counting of counter
For determining the phase difference of the first clock and second clock, phase difference and T1 for determining that the transmission to be measured in path to be measured is prolonged
When.
Further, the first clock, second clock, the first d type flip flop, the second d type flip flop, counter, Edge check list
Member and signal receive determination unit and are integrated in monolithic fpga chip.
Further, edge synchronization detection unit includes: third d type flip flop, four d flip-flop and the 5th d type flip flop,
Third d type flip flop and four d flip-flop are driven by the first clock and second clock respectively；Third d type flip flop and four d flip-flop
The port Q pass through phase inverter and take back the port D, the port D and the port CLK of the 5th d type flip flop be respectively connected to third d type flip flop and
The port Q of four d flip-flop；
The signal that 5th d type flip flop is exported for receiving third d type flip flop and four d flip-flop respectively, and with second
Signal controls the signal itself exported based on the received for the Forward on the efficient clock edge of clock；5th d type flip flop institute is defeated
Signal out be used to indicate at the time of overturning by high level signal to low level signal the first clock and second clock it is effective when
At the time of clock is along alignment.
Further, it includes: XOR gate and the 6th D touching for receiving the signal that XOR gate exports that signal, which receives determination unit,
Device is sent out, the 6th d type flip flop is driven by second clock；XOR gate is respectively connected to the port D and the port Q of the second d type flip flop；
XOR gate is used to receive the D port signal and Q port signal of the second d type flip flop from the second d type flip flop, and at the end D
Message number and Q port signal do not export high level signal simultaneously；
6th d type flip flop is used to export receiving the high level signal of XOR gate output and being triggered by second clock
High level signal；6th d type flip flop is used to indicate the second d type flip flop at the time of exporting high level signal and persistently receives the first D
At the time of when the signal terminating that trigger sends over.
Further, further includes: the path both ends to be measured between the first d type flip flop and the second d type flip flop are accessed
Switch；
Counter is used for respectively in the case where switch on and off, with the moment determined by edge synchronization detection unit
For count initial time, and with signal receive determination unit determined by the moment be count end time, it is defeated to second clock
Signal out is counted, and is obtained the first counting and second and counted；First counting and the second counting are respectively used to determine first
The first phase difference and second phase of clock and second clock are poor, and first phase difference and second phase difference are respectively used to determine with T1
The first transmission delay and the second transmission delay between first d type flip flop and the second d type flip flop, the first transmission delay and second pass
The difference of defeated delay is the transmission delay to be measured in path to be measured.
The invention has the benefit that
The present invention provides a kind of transmission delay test method and device based on FPGA, in the prior art based on most
Mal-condition emulates resulting maximum transmitting time delay information has biggish safe clearance, caused FPGA core compared with practical
Piece is unable to give full play the defect of service performance, and being somebody's turn to do the transmission delay test method based on FPGA includes: to be driven by the first clock
Dynamic first d type flip flop carries out the alternating output of low level signal and high level signal, and drives the 2nd D triggering by second clock
Device carries out the reception for the signal that the first d type flip flop is exported；The period of first clock is T1, and the period of second clock is T2, T1
Greater than T2；Control counter is with the efficient clock of the first clock and second clock determined by edge synchronization detection unit along alignment
At the time of for count initial time, and with signal receive determination unit determined by the second d type flip flop persistently receive the first D
To count end time at the time of when the signal terminating that trigger sends over, the signal of second clock output is counted；
The phase difference and T1 of the first clock and second clock according to determined by the counting as counter, determine the first d type flip flop with
The transmission delay to be measured in the path to be measured between the second d type flip flop.It is constantly tightened by the different clock simulation of two periods
Two clock phases, and time interval of the fast clock acquisition less than slow clock signal is aligned to according to two clock efficient clocks edges
The phase difference of interior two clocks, and the period of slow clock determine the transmission delay of circuit under test, effectively improve transmission and prolong
When the accuracy tested, enable user rationally to reduce design margin in FPGA application, fpga chip can be given full play to
Service performance.
Detailed description of the invention
Fig. 1 is the basic flow chart for the transmission delay test method that the embodiment of the present invention one provides；
Fig. 2 is the waveform modelling figure for the edge synchronization detection unit that the embodiment of the present invention one provides；
Fig. 3 is transmission delay test method basic flow chart provided by Embodiment 2 of the present invention；
Fig. 4 is the structural schematic diagram for the transmission delay test device that the embodiment of the present invention three provides；
Fig. 5 is the structural schematic diagram for the edge synchronization detection unit that the embodiment of the present invention three provides；
Fig. 6 is the waveform diagram that the embodiment of the present invention three provides.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiment is a part of the embodiment in the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Further annotation explanation now is made to the present invention by way of specific embodiment combination attached drawing.
Embodiment one:
To solve to emulate resulting maximum transmitting time delay information tool compared with practical based on most severe condition in the prior art
There is biggish safe clearance, caused fpga chip is unable to give full play the defect of service performance, present embodiments provides one
Transmission delay test method of the kind based on FPGA, as shown in Figure 1 the transmission delay test to be provided in this embodiment based on FPGA
The basic flow chart of method, the transmission delay test method specifically includes the following steps:
S101, the alternating of the first d type flip flop progress low level signal and high level signal is driven to export by the first clock,
And the reception for the signal that the first d type flip flop is exported is carried out by second clock the second d type flip flop of driving；The period of first clock
For T1, the period of second clock is T2, and T1 is greater than T2.
Specifically, inputting two periods different clock, the absolute value of the difference in the period of the two clocks in the present embodiment
Namely the transmission delay measuring accuracy in the present embodiment, wherein the cycle T 1 of the first clock CLK1 is larger, it is slow clock, and second
The cycle T 2 of clock CLK2 is relatively small, is fast clock, wherein when the absolute value of general T1-T2 is sufficiently small, can achieve very high
Transmission delay measuring accuracy.In addition, two clocks in the present embodiment have respectively driven a d type flip flop (data flip-
Flop or delayflip-flop), there is data-in port (port D) on d type flip flop, the data latch output mouth (end Q
Mouthful) and input end of clock mouth (port CLK), wherein CLK1 is for driving the first d type flip flop FF1 output signal, and CLK2 is then
For driving the second d type flip flop FF2 to receive the data of the first d type flip flop FF1 output, the working principle of d type flip flop are as follows: work as clock
When the rising edge of signal arrives, the data of the port D will be passed to the port Q and the non-port Q, here, the port Q and the non-port Q in addition to
Except reverse phase, other characteristics are all identical.CLK1 and CLK2 in the present embodiment export clock signal simultaneously, between the two
Phase phase difference T1-T2, to simulate two clock phases constantly tightened by CLK1 and CLK2.It should be noted that this
The port Q of the first d type flip flop FF1 in embodiment takes back the port D of the trigger by a phase inverter, by phase inverter conduct
The first d type flip flop FF1 alternately 0,1 signal of output can be realized in the phase bit flipping 180 degree of signal by shaping circuit in this way, namely
Low level signal and high level signal.
It should be noted that being accessed in FF1 and FF2 in the present embodiment is path to be measured, the port the Q institute of FF1 is defeated
Signal out is delayed by one section and reaches the port D of FF2 and be received, and the transmission delay of signal is as to be measured in this section of path
Transmission delay (propagation delay).
S102, control counter are with the efficient clock of the first clock and second clock determined by edge synchronization detection unit
It is counting initial time at the time of along alignment, and the second d type flip flop determined by determination unit is received with signal and is persistently received
To count end time at the time of when the signal terminating sended over to the first d type flip flop, to the signal of second clock output into
Row counts.
Specifically, edge synchronization detects namely the detection of rising edge and failing edge, control edge synchronization inspection in the present embodiment
The efficient clock of unit detection two clocks of CLK1 and CLK2 is surveyed along being whether rising edge is aligned, edge synchronization detection unit makes
It is the current value for the clock CLK1 for going frequency acquisition slower using the efficient clock edge of the faster clock CLK2 of frequency with principle,
The level value that acquisition CLK1 is removed using CLK2, with the Forward on the efficient clock edge of CLK2, edge synchronization detection unit can week
The quantity of 0 and 1 equal value of the number of output of phase property, every section exported 0 and 1 is T1/2/ (T1-T2), and at two
When the efficient clock of clock is along alignment, the output of edge synchronization detection unit is 0 by 1 jump, namely is turned to low electricity by high level
It is flat, and the pulse of a failing edge is exported, the phase difference of two clocks is T1-T2 at this time.
Optionally, edge synchronization detection unit includes: third d type flip flop, four d flip-flop and the 5th d type flip flop, and
3d flip-flop and four d flip-flop are driven by the first clock and second clock respectively；Is received respectively by the 5th d type flip flop
The signal of 3d flip-flop and four d flip-flop output, and before the 5th d type flip flop is with the efficient clock edge of second clock
It moves, when signal controls the signal that itself is exported and overturn by high level signal to low level signal based on the received, determines
At the time of current time is aligned for the efficient clock of the first clock and second clock edge.
Specifically, edge synchronization detection unit in the present embodiment includes three d type flip flops, third d type flip flop FF3 and the
The port Q of four d flip-flop FF4 passes through phase inverter and takes back the port D, and the port D and the port CLK of the 5th d type flip flop FF5 connects respectively
Enter the port Q of third d type flip flop FF3 and four d flip-flop FF4.Wherein, FF3 and FF4 uses CLK1 and CLK2 to drive respectively,
Phase inverter is used as frequency divider, this is to be able to the port D of the clock signal access d type flip flop of Clock Tree.FF5's
The port CLK connects the port Q of FF4, and the port D connects the port Q of FF3, i.e. FF5 is to acquire clock using the clock CLK2 after frequency dividing
The signal of CLK1, it should be appreciated that the efficient clock edge of CLK1 and CLK2 alignment the moment and frequency dividing after clock CLK1 ' and
The alignment moment on the efficient clock edge of CLK2 ' is identical.Fig. 2 is the waveform of edge synchronization detection unit provided in this embodiment
Simulation drawing, CLK1 ' and CLK2 ' are the clocks after CLK1 and CLK2 frequency dividing, as shown in Figure 2 it is found that as time goes by, CLK1 and
The phase shift of CLK2 is constantly tightened, and FF5 can periodically export 0,1 equal signal of number, at the time of it is 0 that output is by 1 jump,
I.e. it is believed that the efficient clock of two clocks is along being alignment at this time, since two clock cycle differ smaller, the edge
Sync detection device has relatively high precision.
In addition, every pass through a cycle, the phase difference between CLK1 and CLK2 will increase T1-T2, thus with the time
Passage, CLK1 and CLK2 have the phase shift that a stepping is T1-T2, then, not with the phase between CLK1 and CLK2
Disconnected tightening is bound to exist sometime, and the second d type flip flop that CLK2 is driven will not acquire CLK1 is driven first
The signal that d type flip flop is exported.
Optionally, it includes: XOR gate and the 6th D triggering for receiving the signal that XOR gate exports that signal, which receives determination unit,
Device, the 6th d type flip flop are driven by second clock；Believed by XOR gate from the port D that the second d type flip flop receives the second d type flip flop
Number and Q port signal, and the 6th d type flip flop receive XOR gate output high level signal and by second clock triggering and
When exporting high level signal, determine that current time is that the second d type flip flop persistently receives the signal that the first d type flip flop sends over
At the time of when termination.
Specifically, XOR gate is respectively connected to the port D and the port Q of the second d type flip flop, XOR gate is used in testing for the 2nd D
Whether the signal of the port D of trigger FF2 is consistent with the signal of the port Q, if be consistent, XOR gate exports low level
Signal, conversely, XOR gate can export high level signal.In addition, in order to avoid the signal directly exported according to XOR gate carries out
FF2 do not receive FF1 output signal at the time of judgement when there is ambiguity, the 6th d type flip flop FF6 in the present embodiment also by
CLK2 driving, for receiving the output signal of the XOR gate before being placed in, and the high level signal for receiving XOR gate output with
And when receiving the clock signal of CLK2 output, FF6 is just triggered and exports high level signal, at this time will for characterizing FF2
The signal that FF1 is exported is not acquired, conversely, showing that FF2 still can be adopted correctly at this time when FF6 exports low level signal
Collect the signal that FF1 is exported.It follows that when the signal difference of the port D of FF2 and the port Q, i.e., the output of FF1 at this time
Signal has reached exactly to the port D of FF2, but can't be collected by FF2, then generates a high level signal by XOR gate,
Using a clock cycle of CLK2, a high level pulse is exported by the port Q of FF6.
It should be noted that introducing a counter in the present embodiment, the efficient clock from two clocks is recorded along right
At the time of neat, a high level pulse cut-off is exported to FF6, the CLK2 signal during this is counted, the every warp of CLK2
A cycle is crossed, then the phase shift tightening T1-T2 between CLK1 and CLK2 can be determined, the number that counter is counted is this
The phase shift number of period.
The phase difference and T1 of S103, the first clock and second clock according to determined by the counting as counter determine
The transmission delay to be measured in the path to be measured between the first d type flip flop and the second d type flip flop.
Specifically, assume to be counted as N when what FF6 one high level pulse hour counter of output was exported, and since FF6 is defeated
Out be the signal of a cycle on FF2 has actually passed N-1 phase shift so that actual phase shift number is N-1, and by
At the time of the efficient clock in two clocks of CLK1 and CLK2 is along alignment, the two has a phase difference, so according to reality
Phase shift number and stepping T1-T2 between the two, can determine that total phase difference of two clocks in the time interval is
N* (T1-T2), the transmission delay that the path to be measured of FF1 to FF2 can then be calculated is T1-N* (T1-T2).
It should be noted that in a preferred embodiment, by the present embodiment the first clock, second clock,
First d type flip flop, the second d type flip flop, counter, edge detecting unit and signal receive determination unit and are integrated in monolithic FPGA
In chip, namely the transmission delay of circuit under test can be realized using the available logical resource inside fpga chip, realize it is simple,
And it can economize on resources.
Optionally, to be measured path both ends of the control counter respectively between the first d type flip flop and the second d type flip flop are connect
Enter in the case that switch on and off, with the effective of the first clock determined by edge synchronization detection unit and second clock
It is counting initial time at the time of clock is along alignment, and the second d type flip flop determined by determination unit is received with signal and is continued
It is to count end time at the time of when receiving the signal terminating that the first d type flip flop sends over, to the letter of second clock output
It number is counted, and obtains the first counting and second and count；Identified first clock and second clock are counted according to by first
First phase difference and T1, determine the first transmission delay between the first d type flip flop and the second d type flip flop, and according to by
Second counts the second phase difference and T1 of identified first clock and second clock, determines that the first d type flip flop and the 2nd D touch
Send out the second transmission delay between device；The difference of first transmission delay and the second transmission delay is determined as the to be measured of path to be measured
Transmission delay.
Specifically, in some embodiments, a switch can also be accessed at the both ends in path to be measured, pass through switch
Disconnection and closure can simulate two different test environment, thus respectively in the case that switch on and off two kinds divide
It Jin Hang not be in the counting in gate time section, to respectively obtain two phase differences in both cases, and then to distinguish
The transmission delay in the case of two kinds is obtained, finally the difference of the transmission delay under two kinds of different situations can be determined as road to be measured
The transmission delay size of diameter, so as to further increase path to be measured transmission delay test accuracy.
The transmission delay test method based on FPGA that the present invention provides a kind of is simulated by two periods different clock
Two clock phases constantly tightened, and fast clock acquisition is aligned to less than slow clock signal according to two clock efficient clocks edges
Time interval in two clocks phase difference, and the period of slow clock determine the transmission delay of circuit under test, effectively mention
The accuracy for having risen transmission delay test enables user rationally to reduce design margin in FPGA application, can give full play to
The service performance of fpga chip.
Embodiment two:
In order to better understand the present invention, the present embodiment tests the transmission delay based on FPGA with a specific example
Method is illustrated, and Fig. 3 is the refinement process for the transmission delay test method based on FPGA that second embodiment of the invention provides
Figure, the transmission delay test method include:
S301, the alternating of the first d type flip flop progress low level signal and high level signal is driven to export by the first clock,
And the reception for the signal that the first d type flip flop is exported is carried out by second clock the second d type flip flop of driving；The period of first clock
For T1, the period of second clock is T2, and T1 is greater than T2.
Two periods different clock, the absolute value of the difference namely this reality in the period of the two clocks are inputted in the present embodiment
The transmission delay measuring accuracy in example is applied, wherein the cycle T 1 of the first clock CLK1 is larger, it is slow clock, and second clock CLK2
Cycle T 2 it is relatively small, be fast clock, wherein when the absolute value of general T1-T2 is sufficiently small, can achieve very high transmission and prolong
When measuring accuracy.Such as the period of CLK1 and CLK2 is set to 100.00ns and 99.99ns, test essence in the present embodiment
Degree is 0.01ns, and the CLK1 and CLK2 in the present embodiment export clock signal simultaneously, and phase phase difference T1-T2 between the two can
The step size for knowing clock phase shift is 0.01ns, to simulate two clock phases constantly tightened by CLK1 and CLK2.
The switch that path both ends to be measured between S302, the first d type flip flop of control and the second d type flip flop are accessed disconnects,
And execute S304.
What the path both ends to be measured between S303, the first d type flip flop of control and the second d type flip flop were accessed closes the switch,
And execute S304.
Both ends access in the present embodiment in path to be measured has a switch, can be simulated by the disconnection of switch and closure
Two different test environment out, respectively in the case that switch on and off two kinds execute subsequent counting process, can be with
Further increase the test accuracy of the transmission delay in path to be measured.
S304, the signal for receiving third d type flip flop and four d flip-flop output respectively by the 5th d type flip flop, and the
Five d type flip flops are with the Forward on the efficient clock edge of second clock, and signal controls the letter itself exported based on the received
When number being overturn by high level signal to low level signal, determine that current time is the efficient clock edge of the first clock and second clock
At the time of alignment；Third d type flip flop and four d flip-flop are driven by the first clock and second clock respectively.
When at the time of S305, control counter being aligned with the efficient clock of the first clock and second clock edge to count starting
It carves, starts to count the signal that second clock exports.
The edge of third d type flip flop FF3, four d flip-flop FF4 and the 5th d type flip flop FF5 composition in the present embodiment are same
Step detection unit is used to detect the efficient clock of two clocks of CLK1 and CLK2 along whether being aligned, used mode be using
CLK2 go acquisition CLK1 level value, with the Forward on the efficient clock edge of CLK2, FF5 can periodic the number of output it is equal
0 and 1 value, at the time of it is 0 that output is by 1 jump, i.e., it is believed that the efficient clock of two clocks is along being alignment at this time, at this time
As count initial time.
S306, the D port signal and Q port signal for receiving the second d type flip flop from the second d type flip flop by XOR gate, and
The high level signal of XOR gate output is received in the 6th d type flip flop and high level signal is exported by second clock triggering
When, at the time of determining that current time is when the second d type flip flop persistently receives the signal terminating that the first d type flip flop sends over；
The signal of XOR gate output is received by the 6th d type flip flop, and the 6th d type flip flop is driven by second clock.
When S307, control counter persistently receive the signal terminating that the first d type flip flop sends over the second d type flip flop
At the time of to count end time, stop the signal that export to second clock and count, and respectively obtain in switch disconnection
In the case of first count, and in the case where closing the switch second count.
Every to pass through a cycle, the phase difference between CLK1 and CLK2 will increase T1-T2, thus over time,
CLK1 and CLK2 has the phase shift that a stepping is T1-T2, then, as the phase between CLK1 and CLK2 is constantly received
Tightly, it is bound to exist sometime, the second d type flip flop FF2 that CLK2 is driven will not acquire the first D that CLK1 is driven
The signal of trigger institute FF1 output.The port D and the port Q of FF2 is respectively connected in the present embodiment, by XOR gate to judge FF2
The port D signal it is whether consistent with the signal of the port Q, if so, XOR gate export low level signal, if it is not, XOR gate export
High level signal.The 6th d type flip flop FF6 in the present embodiment is also driven by CLK2, in the high level for receiving XOR gate output
Signal and receive CLK2 output clock signal when, FF6 is just triggered and exports high level signal, for characterize FF2 this
When will not acquire the signal that FF1 exported, be at this time to count end time.
It is assumed that, when FF6 exports high level signal, counter is counted as N1, is switching in the case where switching disconnection
In the case where disconnection, when FF6 exports high level signal, counter is counted as N2, and what it is due to FF6 output is FF2 upper one
The signal in period so that actual phase shift number is respectively N1-1 and N2-1, however is counting between two clocks of initial time i.e.
There is a phase difference, so total phase shift difference is respectively N1* (T1-T2) and N2* (T1-T2), continues to accept aforementioned citing, namely
Respectively 0.01*N1 and 0.01*N2.
The first phase difference and T1 that S308, basis count identified first clock and second clock by first, determine
The first transmission delay between first d type flip flop and the second d type flip flop, and identified first clock is counted according to by second
With the second phase difference and T1 of second clock, the second transmission delay between the first d type flip flop and the second d type flip flop is determined.
S309, the transmission delay to be measured that the difference of the first transmission delay and the second transmission delay is determined as to path to be measured.
Continue to accept aforementioned citing, namely the first transmission delay in the case where switching disconnection is 100-0.01*N1, and
The second transmission delay in the case where closing the switch is 100-0.01*N2, so that the transmission delay to be measured in path to be measured is then
The absolute value of 0.01* (N2-N1).
The transmission delay test method based on FPGA that the present invention provides a kind of is simulated by two periods different clock
Two clock phases constantly tightened, and fast clock acquisition is aligned to less than slow clock signal according to two clock efficient clocks edges
Time interval in two clocks phase difference, and the period of slow clock determine the transmission delay of circuit under test, effectively mention
The accuracy for having risen transmission delay test enables user rationally to reduce design margin in FPGA application, can give full play to
The service performance of fpga chip.
Embodiment three:
A kind of transmission delay test device based on FPGA is present embodiments provided, specifically refers to Fig. 4, comprising: first
Clock 41, second clock 42, the first d type flip flop 43, the second d type flip flop 44, counter 45, edge synchronization detection unit 46 and
Signal receives determination unit 47, and path 48 to be measured is accessed between the first d type flip flop 43 and the second d type flip flop 44；First d type flip flop
43 port Q takes back the port D by phase inverter, and the period of the first clock 41 is T1, and the period of second clock 42 is T2, and T1 is greater than
T2；The alternating output that first clock 41 is used to that the first d type flip flop 43 to be driven to carry out low level signal and high level signal；When second
The reception that clock 42 is used to that the second d type flip flop 44 to be driven to carry out the signal that the first d type flip flop 43 is exported；Edge synchronization detection unit
46 for determining the efficient clock of the first clock 41 and second clock 42 along alignment at the time of；Signal receives determination unit 47 and is used for
At the time of determination when the second d type flip flop 44 persistently receives the signal terminating that the first d type flip flop 43 sends over；Counter 45 is used
In being to count initial time, and receive the institute of determination unit 47 really with signal with the moment determined by edge synchronization detection unit 46
To count end time at the time of determining, the signal exported to second clock 42 is counted；The counting of counter 45 is for determining
The phase difference of first clock 41 and second clock 42, phase difference and T1 are used to determine the transmission delay to be measured in path 48 to be measured.
Specifically, inputting two periods different clock, the absolute value of the difference in the period of the two clocks in the present embodiment
Namely the transmission delay measuring accuracy in the present embodiment is slow clock wherein the cycle T 1 of the first clock 41 is larger, and when second
The cycle T 2 of clock 42 is relatively small, is fast clock, wherein when the absolute value of general T1-T2 is sufficiently small, can achieve very high biography
Defeated delay test precision.The first clock 41 in the present embodiment exports clock signal with second clock 42 simultaneously, between the two
Phase phase difference T1-T2, to simulate two clock phases constantly tightened with second clock 42 by the first clock 41.It should
Illustrating, the port Q of the first d type flip flop 43 in the present embodiment takes back the port D of the trigger by a phase inverter, this
The first d type flip flop 43 alternately 0,1 signal of output namely low level signal and high level signal can be realized in sample.In addition, this implementation
Being accessed in the first d type flip flop 43 and the second d type flip flop 44 in example is path 48 to be measured, the port Q of the first d type flip flop 43
The signal exported reaches the port D of the second d type flip flop 44 and is received, the biography of signal in this section of path by one section of delay
Defeated delay is transmission delay (propagation delay) to be measured.
In addition, when controlling first clock of the detection of edge synchronization detection unit 46 41 in the present embodiment with second clock 42 two
For the efficient clock of clock along being whether rising edge is aligned, the use principle of edge synchronization detection unit 46 is when using frequency faster
The current value for the first clock of clock 41 that the efficient clock edge of clock second clock 42 goes frequency acquisition slower, namely when use second
Clock 42 removes the level value of the first clock 41 of acquisition, and with the Forward on the efficient clock edge of second clock 42, edge synchronization detection is single
0 and 1 equal value of the 46 periodic the number of output of meeting of member, and when the efficient clock of two clocks is along alignment, edge synchronization
The output of detection unit 46 is 0 by 1 jump, namely is turned to low level by high level, and exports the pulse of a failing edge, and
Using this moment as detection phase shift number purpose initial time.Also, it is every to pass through a cycle, the first clock 41 and second clock 42
Between phase difference will increase T1-T2, thus over time, the first clock 41 has a stepping with second clock 42
For the phase shift of T1-T2, then, as the phase between the first clock 41 and second clock 42 is constantly tightened, it is bound to deposit
Sometime, the second d type flip flop 44 that second clock 42 is driven will not acquire the first D that the first clock 41 is driven
The signal that trigger 43 is exported, so that receiving determination unit 47 by signal receives row come the signal to this second d type flip flop 44
To be detected, and work at the time of identified second d type flip flop 44 is not acquired the signal that the first d type flip flop 43 exported
To detect phase shift number purpose end time.
It should also be noted that first clock 41 and second according to determined by the counting as counter 45 in the present embodiment
The phase difference and T1 of clock 42 determine the biography to be measured in the path to be measured 48 between the first d type flip flop 43 and the second d type flip flop 44
Defeated delay.If counter is counted as N, transmission delay to be measured is then T1-N* (T1-T2).
It should be noted that in a preferred embodiment, by the first clock 41, the second clock in the present embodiment
42, the first d type flip flop 43, the second d type flip flop 44, counter 45, edge synchronization detection unit 46 and signal, which receive, determines list
Member 47 is integrated in monolithic fpga chip, namely circuit under test 48 can be realized using the available logical resource inside fpga chip
Transmission delay, realize simple, and can economize on resources.
In preferred example a kind of in the present embodiment, referring to Fig. 5, Fig. 5 is edge synchronization provided in this embodiment inspection
The structural schematic diagram of unit is surveyed, edge synchronization detection unit 46 includes: third d type flip flop 461, four d flip-flop 462 and the
Five d type flip flops 463, third d type flip flop 461 and four d flip-flop 462 are driven by the first clock 41 and second clock 42 respectively；
The port Q of third d type flip flop 461 and four d flip-flop 462 passes through phase inverter and takes back the port D, the D of the 5th d type flip flop 463
Port and the port CLK are respectively connected to the port Q of third d type flip flop 461 and four d flip-flop 462.Wherein, the 5th d type flip flop
463 signals exported for receiving third d type flip flop 461 and four d flip-flop 462 respectively, and having with second clock 42
Signal controls the signal itself exported based on the received for the Forward on effect clock edge；The letter that 5th d type flip flop 463 is exported
The efficient clock of the first clock 41 and second clock 42 is used to indicate at the time of number overturning by high level signal to low level signal
At the time of along alignment.
In preferred example a kind of in the present embodiment, please continue to refer to Fig. 4, it includes: different that signal, which receives determination unit 47,
Or the 6th d type flip flop 472 of door 471 and the signal of the reception output of XOR gate 471, the 6th d type flip flop 472 is by second clock 41
Driving；XOR gate 471 is respectively connected to the port D and the port Q of the second d type flip flop 44.Wherein, XOR gate 471 is used to touch from the 2nd D
D port signal and Q port signal that device 44 receives the second d type flip flop 44 are sent out, and when D port signal is with Q port signal difference
Export high level signal；6th d type flip flop 472 be used for receive XOR gate 471 output high level signal and by second
Clock 42 triggers and exports high level signal；6th d type flip flop 472 is used to indicate the 2nd D touching at the time of exporting high level signal
At the time of when hair device 44 persistently receives the signal terminating that the first d type flip flop 43 sends over.
The first d type flip flop 43 in preferred example a kind of in the present embodiment, please continue to refer to Fig. 4, in the present embodiment
48 both ends of path to be measured between the second d type flip flop 44, which are also accessed, switch 49, to pass through the disconnection and closure of switch 49
Two different test environment can be simulated.And counter 45 is then used for respectively in the opening and closing of situation of switch 49,
It is to count initial time, and determination unit 47 is received with signal and is determined with the moment determined by edge synchronization detection unit 46
At the time of for count end time, to second clock 42 export signal count, and obtain the first counting and second count；
First counting and the second counting are respectively used to determine that the first phase difference and second phase of the first clock 41 and second clock 42 are poor,
First phase difference and second phase difference are respectively used to determine first between the first d type flip flop 43 and the second d type flip flop 44 with T1
The difference of transmission delay and the second transmission delay, the first transmission delay and the second transmission delay is the transmission to be measured in path 48 to be measured
Delay.
It is illustrated in figure 6 waveform diagram provided in this embodiment, as can be seen from Figure, when edge synchronization detection unit
In the 5th d type flip flop the port Q output when being turned to low level by high level, the efficient clock of the first clock and second clock
Along being alignment, T1, T2 in figure are respectively corresponded, the phase difference of the two clocks is the T1-T2 moment at this time.At the time of T4 is corresponded to
It is that signal is emitted by the first d type flip flop, by circuit under test, at the time of reaching the second d type flip flop just, the 2nd D is triggered at this time
The port D of device is different with the signal of the port Q, a high level signal can be generated by XOR gate, using the one of second clock
A clock cycle exports high level signal by the port Q of the 6th d type flip flop, which corresponds to the T3 moment in figure.N in figure
Expression is counted by output signal of the counter to the second clock 42 between T1 the and T3 moment, the number counted.
The transmission delay test device based on FPGA that the present invention provides a kind of is simulated by two periods different clock
Two clock phases constantly tightened, and by edge synchronization detection unit determine the efficient clock of two clocks along alignment when
At the time of carving, and determine fast clock acquisition less than slow clock signal by signal reception determination unit, then according to by counter
It is counted in two clock efficient clocks along the number counted in time interval of the fast clock acquisition less than slow clock signal is aligned to
The phase difference of two clocks is calculated, then the phase difference by being calculated determines that the transmission of circuit under test is prolonged in conjunction with the period of slow clock
When, the accuracy of transmission delay test is effectively improved, user is enabled rationally to reduce design margin in FPGA application, it can
Give full play to the service performance of fpga chip.
The above content is specific embodiment is combined, further detailed description of the invention, and it cannot be said that this hair
Bright specific implementation is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, it is not taking off
Under the premise of from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to protection of the invention
Range.
Claims (10)
1. a kind of transmission delay test method based on FPGA, which is characterized in that the transmission delay test side based on FPGA
Method includes:
It drives the first d type flip flop to carry out the alternating output of low level signal and high level signal by the first clock, and passes through the
Two clocks the second d type flip flop of driving carries out the reception for the signal that first d type flip flop is exported；The period of first clock
For T1, the period of the second clock is T2, and the T1 is greater than T2；
Control counter is with the efficient clock of first clock and the second clock determined by edge synchronization detection unit
It is counting initial time at the time of along alignment, and second d type flip flop determined by determination unit is received with signal and is continued
It is to count end time at the time of when receiving the signal terminating that first d type flip flop sends over, to the second clock
The signal of output is counted；
The phase difference of first clock according to determined by the counting as the counter and the second clock and described
T1 determines the transmission delay to be measured in the path to be measured between first d type flip flop and second d type flip flop.
2. transmission delay test method as described in claim 1, which is characterized in that first clock, second clock, first
D type flip flop, the second d type flip flop, counter, edge detecting unit and signal receive determination unit and are integrated in monolithic fpga chip
In.
3. transmission delay test method as described in claim 1, which is characterized in that the edge synchronization detection unit includes:
Third d type flip flop, four d flip-flop and the 5th d type flip flop, the third d type flip flop and the four d flip-flop respectively by
First clock and second clock driving；
The control counter is effective with first clock determined by edge synchronization detection unit and the second clock
It is counting initial time at the time of clock is along alignment, and second d type flip flop determined by determination unit is received with signal
It is to count end time at the time of when persistently receiving the signal terminating that first d type flip flop sends over, to described second
The signal of clock output count
Receive the signal of the third d type flip flop and four d flip-flop output respectively by the 5th d type flip flop, and
In the 5th d type flip flop with the Forward on the efficient clock edge of the second clock, signal is controlled certainly based on the received
When the signal that body is exported is overturn by high level signal to low level signal, determine that current time is first clock and described
At the time of the efficient clock of second clock is along alignment；
When at the time of control counter being aligned with the efficient clock of first clock and second clock edge to count starting
It carves, and second d type flip flop determined by determination unit is received with signal and persistently receives the first d type flip flop transmission
To count end time at the time of when the signal terminating to come over, the signal of second clock output is counted.
4. transmission delay test method as described in claim 1, which is characterized in that the signal receives determination unit and includes:
XOR gate and the 6th d type flip flop for receiving the signal that the XOR gate exports, the 6th d type flip flop is by the second clock
Driving；
The control counter is effective with first clock determined by edge synchronization detection unit and the second clock
It is counting initial time at the time of clock is along alignment, and second d type flip flop determined by determination unit is received with signal
It is to count end time at the time of when persistently receiving the signal terminating that first d type flip flop sends over, to described second
The signal of clock output count
Control counter is with the efficient clock of first clock and the second clock determined by edge synchronization detection unit
Start to count the signal that the second clock exports to count initial time at the time of along alignment；
The D port signal and Q port signal of second d type flip flop are received from second d type flip flop by the XOR gate,
And the high level signal of XOR gate output is received in the 6th d type flip flop and is triggered and defeated by the second clock
Out when high level signal, determine that current time persistently receives first d type flip flop for second d type flip flop and sends over
Signal terminating when at the time of；
It controls the counter and the signal end that first d type flip flop sends over is received persistently with second d type flip flop
To count end time at the time of when only, and the signal for stopping exporting the second clock counts.
5. transmission delay test method according to any one of claims 1 to 4, which is characterized in that the control counter
It is at the time of with the efficient clock of first clock and the second clock determined by edge synchronization detection unit along alignment
Initial time is counted, and second d type flip flop determined by determination unit is received with signal and persistently receives the first D
To count end time at the time of when the signal terminating that trigger sends over, the signal of second clock output is counted
Number includes:
To be measured path both ends of the control counter respectively between first d type flip flop and second d type flip flop are accessed
In the case that switch on and off, with first clock and the second clock determined by edge synchronization detection unit
Efficient clock along alignment at the time of for count initial time, and with signal receive determination unit determined by the 2nd D
It is to count end time at the time of when trigger persistently receives the signal terminating that first d type flip flop sends over, to institute
The signal for stating second clock output is counted, and is obtained the first counting and second and counted；
The phase difference of first clock determined by the counting according to as the counter and the second clock and
The T1 determines that the transmission delay to be measured in the path to be measured between first d type flip flop and second d type flip flop includes:
According to by described first count determined by the first phase difference of first clock and the second clock and described
T1 determines the first transmission delay between first d type flip flop and second d type flip flop, and according to by described second
The second phase of first clock determined by counting and second clock difference and the T1 determine the first D touching
Send out the second transmission delay between device and second d type flip flop；
The transmission to be measured that the difference of first transmission delay and second transmission delay is determined as the path to be measured is prolonged
When.
6. a kind of transmission delay test device based on FPGA characterized by comprising the first clock, second clock, the first D
Trigger, the second d type flip flop, counter, edge synchronization detection unit and signal receive determination unit, the first D triggering
Path to be measured is accessed between device and the second d type flip flop；The port Q of first d type flip flop takes back the port D, institute by phase inverter
The period for stating the first clock is T1, and the period of the second clock is T2, and the T1 is greater than T2；
The alternating output that first clock is used to that first d type flip flop to be driven to carry out low level signal and high level signal；
The reception that the second clock is used to that second d type flip flop to be driven to carry out the signal that first d type flip flop is exported；
The edge synchronization detection unit is used to determine the efficient clock edge alignment of first clock and the second clock
Moment；
The signal receives determination unit and sends for determining that second d type flip flop persistently receives first d type flip flop
At the time of when the signal terminating to come over；
The counter is used to the moment determined by the edge synchronization detection unit be counting initial time, and with described
Signal receives the moment determined by determination unit to count end time, counts to the signal of second clock output；
The counting of the counter is for determining the phase difference of first clock and the second clock, the phase difference and described
T1 is used to determine the transmission delay to be measured in the path to be measured.
7. transmission delay test device as claimed in claim 6, which is characterized in that first clock, second clock, first
D type flip flop, the second d type flip flop, counter, edge detecting unit and signal receive determination unit and are integrated in monolithic fpga chip
In.
8. transmission delay test device as claimed in claim 6, which is characterized in that the edge synchronization detection unit includes:
Third d type flip flop, four d flip-flop and the 5th d type flip flop, the third d type flip flop and the four d flip-flop respectively by
First clock and second clock driving；The port Q of the third d type flip flop and the four d flip-flop passes through
Phase inverter takes back the port D, and the port D and the port CLK of the 5th d type flip flop are respectively connected to the third d type flip flop and described
The port Q of four d flip-flop；
5th d type flip flop is used to receive the signal of the third d type flip flop and four d flip-flop output respectively, and
As the signal based on the received that moves forward on the efficient clock edge of the second clock controls the signal itself exported；It is described
The signal that 5th d type flip flop is exported is used to indicate first clock at the time of overturning by high level signal to low level signal
At the time of alignment with the efficient clock edge of the second clock.
9. transmission delay test device as claimed in claim 6, which is characterized in that the signal receives determination unit and includes:
XOR gate and the 6th d type flip flop for receiving the signal that the XOR gate exports, the 6th d type flip flop is by the second clock
Driving；The XOR gate is respectively connected to the port D and the port Q of second d type flip flop；
The XOR gate is used to receive the D port signal and Q port signal of second d type flip flop from second d type flip flop,
And high level signal is not exported simultaneously in the D port signal and the Q port signal；
6th d type flip flop is used for when receiving the high level signal of the XOR gate output and by described second
Clock triggers and exports high level signal；The 2nd D touching is used to indicate at the time of the 6th d type flip flop output high level signal
At the time of when hair device persistently receives the signal terminating that first d type flip flop sends over.
10. the transmission delay test device as described in any one of claim 6 to 9, which is characterized in that further include: described
The switch that path both ends to be measured between first d type flip flop and second d type flip flop are accessed；
The counter for respectively it is described switch on and off in the case where, really with edge synchronization detection unit institute
It is counting initial time at the time of determining, and with the moment determined by signal reception determination unit to count end time,
The signal of second clock output is counted, and obtains the first counting and second and counts；It is described first count and it is described
Second counts and is respectively used to determine that the first phase difference and second phase of first clock and the second clock are poor, and described the
One phase difference and the second phase difference are respectively used to determine first d type flip flop and second d type flip flop with the T1
Between the first transmission delay and the second transmission delay, the difference of first transmission delay and second transmission delay is institute
State the transmission delay to be measured in path to be measured.
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| CN111812490A (en) * | 2019-04-12 | 2020-10-23 | 上海复旦微电子集团股份有限公司 | Method for testing signal transmission delay in FPGA chip |
| CN112816858A (en) * | 2020-12-31 | 2021-05-18 | 成都华微电子科技有限公司 | Digital circuit delay test method, test circuit and integrated circuit chip |
| CN113188372A (en) * | 2021-04-02 | 2021-07-30 | 绵阳慧视光电技术有限责任公司 | Method and device for measuring processing delay time of optical seeker |
| CN113377060A (en) * | 2021-08-13 | 2021-09-10 | 成都博宇利华科技有限公司 | Method for acquiring sampling time of each sampling point in signal acquisition system |
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| CN117787168A (en) * | 2023-11-15 | 2024-03-29 | 北京国科天迅科技股份有限公司 | FPGA speed grade determining method and device and electronic equipment |
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| CN114691583A (en) * | 2020-12-30 | 2022-07-01 | 意法半导体国际有限公司 | Data bridge for interfacing source synchronous data paths with unknown clock phases |
| US11989148B2 (en) | 2020-12-30 | 2024-05-21 | Stmicroelectronics International N.V. | Data bridge for interfacing source synchronous datapaths with unknown clock phases |
| CN112816858A (en) * | 2020-12-31 | 2021-05-18 | 成都华微电子科技有限公司 | Digital circuit delay test method, test circuit and integrated circuit chip |
| CN112816858B (en) * | 2020-12-31 | 2022-09-16 | 成都华微电子科技股份有限公司 | Digital circuit delay test method, test circuit and integrated circuit chip |
| CN113188372A (en) * | 2021-04-02 | 2021-07-30 | 绵阳慧视光电技术有限责任公司 | Method and device for measuring processing delay time of optical seeker |
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