CN205991813U - The list realizing multichannel low frequency pick-up signals collecting interrupts CPU verification system - Google Patents

Abstract

Present patent application provides a kind of list realizing multichannel low frequency pick-up signals collecting interrupts CPU verification system, the system composition includes gathering pick-up branch road and by containing single CPU interrupting piece of tissue, DI module containing hardware interrupts and the control system of DO module composition, the interrupt request singal line of DI module is connected with cpu data bus, its enumerator is delivered on output of pulse signal line one tunnel in each tested portion, another Lu Jingqi time-shared switch is connected with DI module one input channel, each road synchronism output line of DO module allows end to be connected with the enumerator of each collection pick-up branch road and timer.The technical program achieves CPU with low technical index allocation, particularly only has the CPU of single hardware interrupts, disposably complete the calibration operation of many low-frequency pulses pick-up signal output sensor or gauge, compare traditional timing calibrating mode device used time be greatly shortened, accurate measurement, improve calibrating efficiency.

Description

The list realizing multichannel low frequency pick-up signals collecting interrupts CPU verification system

Technical field

Present patent application refers to multiple sensor or gauge assay device, more particularly, to collection sensing pick-up The assay device of the multiple sensor of output low frequency pulse signal.

Background technology

The sensor of pick-up output low frequency pulse signal or gauge product category are various, mainly include effusion meter, speed Degree sensor etc., periodic verification sensor is the premise of accurate metering.Current assay device still once to examine and determine based on one, But current satisfaction disposably completes multiple stage sensor or the assay device of the such specific demand of gauge, in the prior art very Few, multiple stage is examined and determine based on the general collection with normal frequency simultaneously, using timing checking method, can produce the error of ± 1 pulse, but right For the output gauge of high-frequency pulse or sensor, within the set time, pulse collection amount is big, ± 1 pulse cause phase Minimum to error, negligible, but for the sensor for output low frequency pulse or chronograph, such as output frequency 1hz, if by 0.2 grade of table, the calibrating time is set as 30s, and lost 1 pulse can cause the larger relative error of 1/30=3.3%, so, Meet high-precision requirement, timing mode has calibrating, and time-consuming, the technical problem of inefficiency.In order to eliminate ± 1 error, in the industry Technology design employs dual time method pulse difference technique.But double time difference methods need 2 timers, one is PLC internal clocking Device, another is plug-in high-resolution timer.One technical requirements of double time difference methods are acquisition pulse rising edges, according to programmable control For device PLC system integrated configuration processed, the 300 series of PLC systems of selection can meet above-mentioned design requirement, but 300 series of PLC systems Only one interruption piece of tissue of CPU, when an interrupt signal with when interrupting identification and just processing, in same piece of tissue, other passages go out Now new interrupt event, will not be triggered immediately, but also will not lose.According to above-mentioned functions, the PLC system of 300 series is most The collection of two-way low frequency pick-up signal can only be realized, more multichannel low frequency pick-up signals collecting then needs technical performance index more simultaneously The PLC system of high CPU core.The number that 400 serial CPU core system hardwares interrupt is relevant with CPU model, is up to 8 Road hardware interrupts, can meet the needs of above-mentioned multichannel calibrating to a certain extent, but just to realizing multichannel low frequency pick-up signal Collection, and increase substantially device performance, not only cost is high, and the other performance of device itself lie on the table, its waste is huge.

Content of the invention

It is many that the goal of the invention of present patent application is to provide a kind of PLC system using 300 serial CPU cores efficiently to complete The list realizing multichannel low frequency pick-up signals collecting that road low frequency pick-up signal disposably gathers Calibration Technology requirement interrupts CPU calibrating System.What present patent application provided realizes the list interruption CPU verification system technical scheme of multichannel low frequency pick-up signals collecting, its master The technology contents wanted are：A kind of list realizing multichannel low frequency pick-up signals collecting interrupts CPU verification system, and system composition inclusion is adopted Collect pick-up branch road and interrupted the CPU of piece of tissue, contained the DI module of hardware interrupts and the control system of DO module composition, often by containing single One collection pick-up branch road includes tested portion, time-shared switch, enumerator and timer, the interrupt request singal line of DI module with Cpu data bus are connected, and its enumerator, another Lu Jingqi time-shared switch are delivered in output of pulse signal line one tunnel in each tested portion It is connected with DI module one input channel, each road synchronism output line of DO module and each collection enumerator of pick-up branch road and timing Device allows end to be connected, and often the enumerator of collection pick-up branch road and timer are connected with cpu data bus and communication bus respectively.Its In, described tested portion is sensor or gauge.

The list realizing multichannel low frequency pick-up signals collecting disclosed in present patent application interrupts CPU verification system technical scheme, Achieve the CPU with low technical index allocation, particularly only there is the CPU of single hardware interrupts, disposably complete many low frequencies arteries and veins Rush pick-up signal output sensor or gauge, such as the sensing of the output low frequency pulse pick-up signal such as effusion meter, velocity sensor Device or the calibration operation of gauge, the technical program is more suitable for the low frequency signal output that frequency is less than below 10Hz, compares biography System timing calibrating the mode device used time be greatly shortened, accurate measurement, improve calibrating efficiency, improve equipment operation effect Rate, has saved hardware configuration cost, and its practical value is high.The technical program is applied to the low frequency pick-up signal output of below 10Hz Sensor or gauge calibrating, compare output be higher than the sensor of low-band signal of more than 10Hz or the inspection of gauge Fixed, its technique effect becomes apparent from and projects.

Brief description

Fig. 1 is that the system of present patent application constitutes structure chart.

The sequential chart of the calibrating acquisition method that Fig. 2 realizes for present patent application.

Specific embodiment

What present patent application provided realizes the list interruption CPU verification system of multichannel low frequency pick-up signals collecting, can apply In the sensor of all kinds of low frequency pick-up signals or the calibrating of gauge, such as effusion meter, velocity sensor etc..The present embodiment is with 5 tunnels The technical program is described in detail as a example the calibrating application of effusion meter.The list that this realizes multichannel low frequency pick-up signals collecting interrupts The system composition of CPU verification system, as shown in figure 1, include collection pick-up branch road and by the CPU containing single interruption piece of tissue, containing hard DI module and the control system of DO module composition that part interrupts, send calibrating from host computer to CPU and start control instruction, described Control system, be programmable controller PLC system in actual the more of selection.Each collection pick-up branch road includes tested flow Meter 1-5, time-shared switch K1～K5, enumerator M1～M5 and timer N1～N5, the output of pulse signal of each tested effusion meter Its enumerator is delivered on line one road, and another Lu Jingqi time-shared switch is connected with DI module one input channel, the interrupt requests of DI module Holding wire is connected with cpu data bus, each road synchronism output line of DO module and each collection enumerator of pick-up branch road and meter When device allow end be connected, often collection pick-up branch road enumerator be connected with cpu data bus and communication bus respectively with timer. In the present embodiment, be provided with host computer, host computer is connected with CPU fieldbus, the timer of each collection pick-up branch road with upper Position machine port is connected.

CPU verification system is interrupted based on the above-mentioned list realizing multichannel low frequency pick-up signals collecting, opens by positive sequence, positive sequence is closed Time sequencing examining and determine, calibrating when this sequentially achieves etc., the calibrating time of each bypass flow meter is close；Can certainly Open the calibrating order of inverted order pass using positive sequence, the first sequence number meter proof time is the longest, during the meter proof of most end sequence number Between relatively short.The technical program realize calibrating acquisition method be：

1. walk, preset adjustment：

CPU receives host computer calibrating order, and CPU will interrupt allowing to switch to forbid, to avoid outside to include each collection pick-up The time-shared switch action of branch road, triggering is interrupted, the carrying out of impact internal adjustment program；It is defined as an inspection by choosing tested effusion meter Fixed set, and adjust the order sequence number 1,2,3,4,5 giving five effusion meters in this calibrating set, confirm that each branch road timesharing is opened Closing K1～K5 is to disconnect original state；

2. the walk, and starts calibrating：

A. by the first collection pick-up branch road time-shared switch K1 closure in calibrating set, connection the first collection pick-up branch road, After the on off states such as of short duration time delay T second are stable, CPU interrupts allowing to switch to allow, and makes DI module be in reception first collection and becomes Send in branch road counting pulse signal state；

B. interrupt processing：

If rising edge of a pulse is to start edge, after DI module receives the rising edge of a pulse signal of the first collection pick-up branch road, Interrupt requests are sent to CPU from its interrupt request singal line, CPU interrupts allowing to switch to forbid, identifies simultaneously, judges this collection The sequence number of pick-up branch road, and control this collection pick-up branch road time-shared switch K1 disconnect, next sequence number collection pick-up branch road timesharing Switch K2 closure, the start-up study intervalometer of short duration time delay T second, CPU mono- aspect was to DO after time-shared switch K2 closure state is stable Module sends synchronous averaging instruction, sends synchronous letter from DO module to the enumerator M1 and timer N1 of this collection pick-up branch road Number, the first sequence number collection pick-up branch road enters calibrating metering state, and on the other hand, CPU interrupts allowing to switch to allow, and makes DI module It is in the second collection pick-up branch road counting pulse signal state receiving the second sequence number, repeat respectively to be adopted one by one by this step method Calibrating metering state sent into by collection pick-up branch road, makes each enumerator and timer enter evaluation state；

3. the walk, and terminates calibrating：

When in calibrating set, the collection pick-up branch road of most end sequence number enters calibrating metering, CPU starts internal timer meter When the T0 second, make calibrating time T1, T2, T3, T4, T5 of each branch road be no less than T0, to meet Calibration Technology requirement.Set Control the time-shared switch K1 closure of the first or last collection pick-up branch road after calibrating time T0, start internal timer, through of short duration After the time delay T second waits time-shared switch K1 stable, interrupt allowing, for allowing, to wait and receive the rising edge of a pulse signal on this road, CPU interrupts allowing to switch to forbid again, and after judging that this road sets sequence number, controls this road time-shared switch K1 disconnection, next sequence number Branch road time-shared switch K2 closes, and sends synchronous averaging instruction from CPU to DO module simultaneously, from DO module to the enumerator on this road and Timer sends synchronizing signal, and this road enumerator and timer stop counting and timing simultaneously, then CPU starts internal clocking simultaneously The device timing T second, after time-shared switch K2 is stable, CPU interrupts allowing to switch to allow again, and waits and receives in the pulse of next branch road Rise along signal, and terminate the calibrating of each collection pick-up branch road successively one by one, finally counter counts value is obtained by CPU.

Claims (3)

1. a kind of list realizing multichannel low frequency pick-up signals collecting interrupts CPU verification system, and system composition includes collection pick-up and props up Road and interrupted the CPU of piece of tissue, contained the DI module of hardware interrupts and the control system of DO module composition by containing single, each collection becomes Branch road is sent to include tested portion, time-shared switch, enumerator and timer, the interrupt request singal line of DI module is total with cpu data Line is connected, and its enumerator, another Lu Jingqi time-shared switch and DI module are delivered in output of pulse signal line one tunnel in each tested portion One input channel is connected, and each road synchronism output line of DO module allows end with the enumerator of each collection pick-up branch road and timer It is connected, often the enumerator of collection pick-up branch road and timer are connected with cpu data bus and communication bus respectively.

2. the list realizing multichannel low frequency pick-up signals collecting according to claim 1 interrupts CPU verification system, and its feature exists It is the sensor of output low frequency pick-up signal or gauge in described tested portion.

3. the list realizing multichannel low frequency pick-up signals collecting according to claim 1 interrupts CPU verification system, and its feature exists Be additionally provided with host computer in the system, host computer is connected with CPU fieldbus, the timer of each collection pick-up branch road with upper Machine port is connected.