CN106324341A - Multichannel signal frequency measurement module based on SoC (system on chip) - Google Patents
Multichannel signal frequency measurement module based on SoC (system on chip) Download PDFInfo
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- CN106324341A CN106324341A CN201610674205.7A CN201610674205A CN106324341A CN 106324341 A CN106324341 A CN 106324341A CN 201610674205 A CN201610674205 A CN 201610674205A CN 106324341 A CN106324341 A CN 106324341A
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
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Abstract
The invention discloses a multichannel signal frequency measurement module based on an SoC (system on chip), and the system on a chip is an SoC (system on chip) chip or a system-level chip. The measurement module facilitates the performing of precise measurement of the frequency of a multichannel signal on a very small area through the high integration degree, also can cooperate with a remote terminal through an extended TCP and carries out the man-machine interaction through an extended touch display screen. The module is characterized in that the module comprises an SoC main controller; the SoC main controller is connected with a power module, a touch control module, and a peripheral interface; the SoC main controller also comprises a main control unit, an auxiliary control unit and an FPGA module, wherein the auxiliary control unit and the FPGA module are respectively connected with the main control unit; the FPGA module is connected with a frequency measurement module; the main control unit is connected with a communication unit; the frequency measurement module is provided with a measured signal interface; the communication module is connected with a remote terminal interface; and the touch control module is provided with a touch display screen interface.
Description
Technical field
The present invention relates to instrument field, a kind of multi channel signals frequency measurement mould based on SOC(system on a chip)
Block, described SOC(system on a chip) i.e. SoC chip or system level chip, this frequency measuring block is conducive to by its high integration the least
Area on realize the accurate measurement of multi channel signals frequency, it is also possible to by TCP and the remote terminal collaborative work of extension, logical
The touch display screen crossing extension carries out man-machine interaction.
Background technology
The high-acruracy survey of frequency can make people more effectively recognize, analyze signal, requires low-power consumption, high-precision at some
Degree frequency measurement occasion, XILINX series SoC can more efficient complete this task, its FPGA frequency can steady operation at 250M
Above, use Equal-precision digital frequency measure method can accurately record the frequency of TTL signal, coordinate ARM system in front-end circuit and sheet,
The functions such as frequency measurement and the result that can complete arbitrary signal show, transmission.The nineties in last century, SoC (System on a
Chip, a kind of by microprocessor, Analog IP core, the numeral integrated one chip such as IP kernel and memorizer, it is also called SOC(system on a chip)
Or system level chip) concept is suggested, SoC can effectively reduce the development cost of electronics/information system product, shortens exploitation week
Phase, improve the competitiveness of product, its purpose is to overcome some difficulties run in multi-chip Integration System Design, shorten each
Time delay between device.Along with the development of SoC technology and perfect, integrated processor, logic device and deposit on a single chip
Reservoir etc., it is possible to complete the collection of signal, process and the function such as transmission, improve the speed of system, reduce hardware configuration
Complexity and overall cost.The SOPC technology realizing SoC function with the FPGA of programming device has been able to ripe embedding
Soft, hard nucleus management device IP, has design flexibly, can cutting, scalable, possess the merit of software and hardware in-system programmable components
Energy.Meanwhile, the FPGA processor of current main flow can also run linux system, facilitate writing of application program, make high collection
The frequency measuring block of Cheng Du becomes possibility.
Summary of the invention
The present invention is directed to defect or deficiency present in prior art, it is provided that a kind of multi channel signals based on SOC(system on a chip)
Frequency measuring block, described SOC(system on a chip) i.e. SoC chip or system level chip, this frequency measuring block is conducive to by its high collection
Cheng Du realizes the accurate measurement of multi channel signals frequency on the least area, it is also possible to by TCP and the remote terminal of extension
Collaborative work, carries out man-machine interaction by the touch display screen of extension.
Technical scheme is as follows:
A kind of multi channel signals frequency measuring block based on SOC(system on a chip), it is characterised in that include SOC(system on a chip) master control
Device processed, described SOC(system on a chip) master controller connects power module, touch-control module and peripheral interface, described SOC(system on a chip) master control respectively
Device processed includes main control unit and the Auxiliary Control Element interconnected respectively and FPGA module, described FPGA module with main control unit
Connecting frequency measurement module, described main control unit connects communication module, and described frequency measurement module has measured signal interface, described communication
Module remote terminal interface, described touch-control module has touch display screen interface.
Described frequency measurement module include in-phase proportion amplifying circuit that front-end circuit, described front-end circuit include being sequentially connected with,
Amplitude limiter circuit, filter amplification circuit and Schmitt trigger circuit, described Schmidt trigger connects described FPGA module.
In-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit and schmidt trigger is included in described frequency measurement module
Device, measured signal first passes through in-phase proportion amplifying circuit, then pass through amplitude limiter circuit the signal of 1～12V is limited in 0.7V with
Under, then input Schmidt trigger is converted into square wave after rear class filter and amplification, now signal amplitude scope meets FPGA's
IO level input range, now utilizes equal precision measurement module to get final product the periodicity of units of measurement this signal gate time.
Include leading to scaling circuit, amplitude limiter circuit, filter amplification circuit and schmidt trigger in described frequency measurement module
Device, measured signal is through in-phase proportion amplifier amplifies signals amplitude so that the range of signal that the conversion of rear class waveform can identify is more
Width, then passes through amplitude limiter circuit and the signal of 1～12V is limited in below 0.7V, then input is executed close after rear class filter and amplification
Special trigger is converted into square wave, and now signal amplitude scope meets the IO level input range of FPGA, now utilizes equally accurate to survey
Amount module can measure the frequency values of this signal.
Described frequency measurement module includes the first operational amplifier, the letter that front-end circuit, described front-end circuit include being sequentially connected with
Number clamp circuit, filter inductance and the second operational amplifier, described second operational amplifier connects Schmidt trigger, described in execute
Schmitt trigger connects described FPGA module.
Described first operational amplifier connects one end and the filter inductance of described signal clamping circuit by the first resistance
The primary nodal point that one end is formed, described signal clamping circuit includes the first clamp diode and the second clamp diode, first
The negative terminal of clamp diode and the anode of the second clamp diode are all connected with described primary nodal point, the anode of the first clamp diode
Being all connected with earth terminal with the negative terminal of the second clamp diode, the other end of described filter inductance connects described the by the second resistance
Two operational amplifiers, and connect earth terminal by the 3rd resistance.
Described main control unit and described Auxiliary Control Element constitute dual core processor, and described dual core processor interconnects respectively
On-chip bus and interface bus, described on-chip bus connects I/O unit, institute by different external bus protocol respectively
Stating interface bus and be interconnected to programmed logical module, described programmed logical module includes field programmable gate array module, number
Word signal processing module, system monitoring module, Peripheral Component Interconnect module and random access memory module, described system monitoring mould
Block and described Peripheral Component Interconnect module are provided with Serial Peripheral Interface (SPI).
Described frequency measurement module is with array distribution, and each frequency measurement module all receives standard signal frequency and measured signal frequency
Rate, described frequency measurement module rate of connections computing divider, described frequency calculation divider utilizes the unit gate after moving to left 32bit
In time, measured signal periodicity is divided by with reference signal periodicity in unit gate time, obtains the quilt relative to reference clock
Survey signal relative frequency value, by this relative frequency value by ordered storage device and transmission channel interface be uploaded to microprocessor or
CPU is to obtain absolute frequency value.
Described remote terminal interface connects remote terminal, and described multi channel signals frequency measuring block is by the TCP of extension
With remote terminal collaborative work；Described touch display screen interface connects touch display screen, to carry out man-machine interaction.
The technique effect of the present invention is as follows: by this multi channel signals frequency measuring block, can monitor multi channel signals frequency
The accurate results of rate, it is also possible to by TCP and the remote terminal collaborative work of extension, by the touch display screen of extension
Carry out man-machine interaction.Relative frequency value on CPU readout data bus, is multiplied by calibrated reference clock frequency value the most available
Accurate measured signal absolute frequency value.CPU also has a lot of peripheral interface, other application expansible.
Accompanying drawing explanation
Fig. 1 is the structural representation implementing a kind of multi channel signals frequency measuring block based on SOC(system on a chip) of the present invention.
Fig. 2 is the front-end circuit schematic diagram in frequency measurement module.
Fig. 3 is SOC(system on a chip) SoC structural representation.SoC refers to system single chip, System-on-a-Chip, and sheet is
System.
Fig. 4 is Equal-precision digital frequency measure principle schematic.
Fig. 5 is frequency measurement calculation process block diagram.
Reference lists as follows: 1-multi channel signals frequency measuring block；2-power module；3-peripheral interface；4-
FPGA module/logic gate array/Field Programmable Gate Array (field programmable gate array module)；5-master
Control unit/Core1 (the first core in polycaryon processor)；6-Auxiliary Control Element/Core2 (the second core in polycaryon processor)；
7-SOC(system on a chip) master controller；8-frequency measurement module；9-communication module；10-touch-control module/other circuit；11 measured signals；12‐
Remote terminal；13 touch display screen；14 frequency calculation dividers/division IP kernel；FsStandard signal frequency；FxMeasured signal
Frequency；NxThe periodicity of tested frequency signal；NsThe periodicity of standard-frequency signal；TwsMeasure time period effective unit lock
The door time；TwaMeasure preset unit gate time time period；T preset gate time；Ts‐Actual gate time；RAM is random
Access memory module/dual port RAM；FIFO ordered storage device；AXI4_Lite transmission channel interface/AXI4 interface communications protocol
Sub-protocol；ARM microprocessor；PS processor system, belongs to microprocessor ARM, and PS is then main by APU
(Application Processor Unit, application processor unit), memory interface (Memory interfaces), IOP
(I/O peripherals, input/output peripheral) and central authorities' interconnection (Central interconnect) composition；AXI-interface leads to
Letter protocol/interface bus；AMBA-advanced microcontroller bus architecture, Advanced Microcontroller Bus
Interconnection specification agreement on Architecture, or sheet, or on-chip bus；PL-programmed logical module, such as FPGA；IO-is defeated
Enter/output unit；SPI-Serial Peripheral Interface (SPI), Serial Peripheral Interface；PCIe-bus interface module,
PCI-Express, PCI, Peripheral Component Interconnect module, Peripheral Component Interconnect；DSP-numeral is believed
Number processing module, Digital Signal Process, dsp chip i.e. refers to realize the chip of Digital Signal Processing；
SysMon-system monitoring module；Various external interface/the external bus protocol of CAN, UART, SDIO, USB, GigE-；U10-first
Operational amplifier；Test-the second operational amplifier；D3-the first clamp diode；D4-the second clamp diode；74HC14-executes
Schmitt trigger；L3-filter inductance；R3-the first resistance；R42-the second resistance；R43-the 3rd resistance；GND-earth terminal.
Detailed description of the invention
Below in conjunction with the accompanying drawings (Fig. 1-Fig. 5) the present invention will be described.
Fig. 1 is the structural representation implementing a kind of multi channel signals frequency measuring block based on SOC(system on a chip) of the present invention.
Fig. 2 is the front-end circuit theory structure schematic diagram in frequency measurement module.Fig. 3 is SOC(system on a chip) SoC structural representation.SoC refers to
System single-chip, System-on-a-Chip, chip system, system level chip, SOC(system on a chip).Fig. 4 is that Equal-precision digital frequency measure is former
Reason schematic diagram.Fig. 5 is frequency measurement calculation process block diagram.As shown in Figures 1 to 5, a kind of manifold based on SOC(system on a chip)
Road signal frequency measurement module 1, including SOC(system on a chip) master controller 7, described SOC(system on a chip) master controller 7 connects power supply mould respectively
Block 2, touch-control module 10 and peripheral interface 3, described SOC(system on a chip) master controller 7 include main control unit 5 and respectively with main control
The Auxiliary Control Element 6 of unit 5 interconnection and FPGA module 4, described FPGA module 4 connects frequency measurement module 8, described main control unit
5 connect communication module 9, and described frequency measurement module 8 has measured signal interface (being used for receiving measured signal 11), described communication module
9 remote terminal interfaces (are used for connecting remote terminal 12), and described touch-control module 10 has touch display screen interface and (is used for connecting tactile
Touch display screen 13).Described frequency measurement module 8 includes that the in-phase proportion that front-end circuit, described front-end circuit include being sequentially connected with amplifies
Circuit (the such as first operational amplifier U10), amplitude limiter circuit, filter amplification circuit (the such as second operational amplifier Test) and execute
Schmitt trigger 74HC14, described Schmidt trigger connects described FPGA module 4.
Voltage follower circuit, amplitude limiter circuit, filter amplification circuit and hysteresis comparator, quilt is included in described frequency measurement module 8
Survey signal and first pass through voltage follower circuit, then pass through amplitude limiter circuit and the signal of 1～12V is limited in below 0.7V, then pass through
Inputting Schmidt trigger 74HC14 after rear class filter and amplification and be converted into square wave, now signal amplitude scope meets the IO electricity of FPGA
Flat input range, now utilizes equal precision measurement module to get final product the periodicity of units of measurement this signal gate time.Or, described
In-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit and Schmidt trigger circuit, in-phase proportion is included in frequency measurement module
Amplifier amplifies signals amplitude so that the rear class waveform range of signal that can identify of conversion is wider, then pass through amplitude limiter circuit by 1～
The signal of 12V is limited in below 0.7V, then after rear class filter and amplification, input Schmidt trigger is converted into square wave, now believes
Number amplitude range meets the IO level input range of FPGA, now utilizes equal precision measurement module can measure the frequency of this signal
Value.
Described frequency measurement module 8 includes that front-end circuit, described front-end circuit include the first operational amplifier being sequentially connected with
U10, signal clamping circuit, filter inductance L3 and the second operational amplifier Test, described second operational amplifier Test connection is executed
Schmitt trigger 74HC14, described Schmidt trigger 74HC14 connect described FPGA module 4.Described first operational amplifier
The first segment that one end of one end and limit frequency inductance L3 that U10 connects described signal clamping circuit by the first resistance R3 is formed
Point, described signal clamping circuit includes the first clamp diode D3 and the second clamp diode D4, the first clamp diode D3's
The anode of negative terminal and the second clamp diode D4 is all connected with described primary nodal point, the anode of the first clamp diode D3 and the second pincers
The negative terminal of position diode D4 is all connected with earth terminal GND, and the other end of described filter inductance L3 connects described by the second resistance R42
Second operational amplifier Test, and connect earth terminal GND by the 3rd resistance R43.Described main control unit 5 and described auxiliary control
Unit 6 processed constitutes dual core processor PS, described dual core processor PS and interconnects on-chip bus AMBA and interface bus AXI, institute respectively
State on-chip bus AMBA respectively by different external bus protocol (such as, SPI, CAN, UART, SDIO, USB, GigE etc.) even
Meet I/O unit IO, described interface bus AXI and be interconnected to programmed logical module PL, described programmed logical module PL
Including field programmable gate array module FPGA, digital signal processing module DSP, system monitoring module SysMon, external components
Interconnecting modules PCIe and random access memory module RAM, described system monitoring module SysMon and described Peripheral Component Interconnect mould
Block PCIe is provided with serial peripheral equipment interface SPI.
Described frequency measurement module 8 is with array distribution, and each frequency measurement module 8 all receives standard signal frequency FsAnd measured signal
Frequency Fx, described frequency measurement module 8 rate of connections computing divider 14, described frequency calculation divider 14 utilizes after moving to left 32bit
Unit gate time in measured signal periodicity NxWith reference signal periodicity N in unit gate timesIt is divided by, obtains relatively
In the measured signal relative frequency value of reference clock, by this relative frequency value by ordered storage device FIFO and transmission channel interface
AXI4_Lite is uploaded to microprocessor ARM or CPU to obtain absolute frequency value.Described remote terminal interface connects remote terminal
12, described multi channel signals frequency measuring block 1 is by the TCP extended and remote terminal 12 collaborative work；Described touch shows
Screen interface connects touch display screen 13, to carry out man-machine interaction.
The present invention provides a kind of high integration frequency measuring block based on SoC, including: master controller, front-end circuit, its
Middle master controller includes main control unit, logic gate array, main control unit can and logic gate array between transmitting and receiving data,
Measured signal accesses logic gate array by frequency measurement module respectively, and the work process of wherein said system is: a) front-end circuit will
FPGA is accessed after measured signal conditioning shaping；B) the measured signal periodicity that FPGA records moves to left 32, reference signal periodicity
Accessing the division IP in DSP, result is uploaded in CPU by data/address bus；C) to obtain this tested by reading device file for CPU
The frequency values of signal, can pass through communication module up to remote terminal, it is also possible to carry out man-machine by the touch display screen of extension
Alternately.Further, wherein, described step a) is implemented as follows, and in frequency measurement module, measuring circuit includes that in-phase proportion is put
Big circuit, amplitude limiter circuit, filter amplification circuit, Schmidt trigger, measured signal first passes through in-phase proportion amplifying circuit, subsequently
Through amplitude limiter circuit, the signal of 1～12V is limited in below 0.7V, then after rear class filter and amplification, inputs Schmidt trigger
Being converted into square wave, now signal amplitude scope meets the IO input range of FPGA, now utilizes equal precision measurement module to survey
The periodicity of amount unit this signal gate time.Further, there is inside FPGA IP kernel, in described b) step, by adjusting
Generate division IP with DSP, base in measured signal periodicity and unit gate time will be moved to left in the unit gate time after 32bit
Calibration signal periodicity is divided by, and obtains the measured signal frequency relative to reference clock, and this relative frequency value is passed through data/address bus
It is uploaded to CPU to obtain absolute frequency value.Further, the relative frequency value on CPU readout data bus, is multiplied by calibrated
Reference clock frequency value i.e. can get accurate measured signal absolute frequency value.Wherein, reference signal frequency value can be by correction
The 10M reference signal of FPGA output obtains.CPU can be by communication interface and remote terminal communication further, it is also possible to passes through
The touch control display module of extension carries out man-machine interaction.Further, CPU also has a lot of peripheral interface, other application expansible.
A kind of high integration frequency measuring block based on SoC, including SoC unit, frequency measurement principle, the frequency of optimization
Calculating transmission principle, front-end circuit, described SoC unit is master controller, and described frequency measurement principle is Equal-precision digital frequency measure
Principle, the frequency of described optimization calculates transmission principle can reduce the utilization rate reducing CPU in the case of ensureing precision.Before described
Terminal circuit completed input signal clamped, amplify, the function of shaping.The work process of wherein said system is: front-end circuit
Input signal is amplified, clamped, filter and amplification, inputs a signal into logic gate array after shaping, it is therefore an objective to signal will be measured
The Transistor-Transistor Logic level that conditioning is measured for being suitable for logic gate array to be suitable for；Measured by the equally accurate frequency measurement module within logic gate array
The periodicity of measured signal and the periodicity of reference signal in unit interval, input after measured signal periodicity moves to left 32bit
Division IP in DSP calculates the precise frequency value of measured signal, and is uploaded to main control unit；Main control unit can read also
Show each channel frequence value or frequency values is sent to remote terminal by interfaces such as networks.Front-end circuit in frequency measurement module
Including in-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit, Schmidt trigger；Measured signal first pass through with compared with
Example amplifying circuit, then passes through amplitude limiter circuit and the signal of 1～12V is limited in below 0.7V, then after rear class filter and amplification
Input Schmidt trigger is converted into square wave, and now signal amplitude scope meets the IO level of programmable gate array (FPGA)
Input range.Described system also includes FPGA, DSP, CPU, and FPGA mainly measures the week of measured signal in unit gate time
Issue, the periodicity of reference signal, DSP is mainly calculated the periodicity of measured signal, is then sent out by frequency values by data/address bus
Deliver to CPU.Described module includes communication module, a scalable network module, peripheral expansion module, touches display screen, main control list
Unit Core1 can be connected with remote terminal by communication module, can interact with intrasystem touching display screen；Assist control list
Unit Core2 can be connected with other circuit peripheral by peripheral expansion module.
The present invention achieves the measurement of signal frequency in the case of ensureing degree of precision with less volume.A kind of based on
The high integration frequency measuring block of SoC, including master controller, front-end circuit.Described master controller i.e. SoC (System on a
Chip, microprocessor, Analog IP core, numeral IP kernel and the integrated one chip of memorizer), complete into the frequency of Transistor-Transistor Logic level signal
Rate measure, calculate, described front-end circuit complete input signal clamped, amplify, the function of shaping.
See Fig. 1, it is shown that frequency measuring block of the present invention, including master controller, frequency measurement module, communication module, periphery
Expansion module, extendible touch display screen etc..Wherein, master controller includes main control unit Core1, Auxiliary Control Element
Core2, logic gate array FPGA, main control unit Core1 can and Auxiliary Control Element Core2 and logic gate array between send
Receive data.And main control unit Core1 can be connected with remote terminal by communication module；Auxiliary Control Element Core2 can
Is connected with other circuit peripheral by peripheral expansion module, and can and the touch display screen extended between receiving and transmitting signal.Tested
Signal accesses FPGA by front-end circuit.Measured signal is converted to the TTL in the range of the IO input capability of FPGA by front-end circuit
Level；
By communication module, the result of calculating can be uploaded to remote terminal, and remote terminal can also be with main control unit
Core1, Auxiliary Control Element Core2, logic gate array FPGA communicate, and adjust gate time, show measurement result, preserve
The data of Real-time Collection are so that the later stage adjusts back, analytical data；Waveform modulate circuit in frequency measurement module includes that in-phase proportion amplifies
Circuit, amplitude limiter circuit, filter amplification circuit, Schmidt trigger；Measured signal first passes through in-phase proportion amplifying circuit, with after warp
Cross amplitude limiter circuit and the signal of 1～12V is limited in below 0.7V, then input Schmidt trigger turns after rear class filter and amplification
Changing square wave into, now signal amplitude scope meets the IO level input range of FPGA.Utilize the equal precision measurement module in FPGA
Can measure and calculate measured signal frequency values.
The work process of described system is described below: measured signal is amplified by (1) front-end circuit, amplitude limit, filtering are put
Greatly, waveform conversion, be adjusted to FPGA IO input range can Transistor-Transistor Logic level, front-end circuit as shown in Figure 2, U10 is by the unknown
The signal of amplitude amplifies 10 times, the output peak signal rail voltage less than U10, by D1, D2 by clamped for signal to ± 0.7V
Scope, the existence of L3 can slacken signal impact during start significantly, and the signal amplification 3 times of amplitude limit is met rear class and executes close by Test
The input reference signal of special trigger, Schmidt trigger can convert the signal into the standard meeting FPGA input range
TTL signal.(2) system architecture diagram of main control unit SoC is as shown in Figure 3, and PS (Processor System) is ARM portion
Point, mainly complete the correction resolving of measurement result, the function such as control realization, result show, transmission, PL (Programmable
Logic) it is FPGA portion, mainly completes frequency measurement and the calculating of Transistor-Transistor Logic level.PS is then main by APU (Application
Processor Unit, application processor unit), memory interface (Memory interfaces), IOP (I/O
Peripherals, input/output peripheral) and central authorities' interconnection (Central interconnect) composition.(3) main control unit
FPGA portion obtains base in the periodicity of measured signal in unit gate time, unit gate time by equally accurate measuring frequency principle
The periodicity of calibration signal, generates division IP kernel by calling DSP, synchronizes to obtain the frequency values relative to reference signal.Equally accurate
As shown in Figure 4, its actual gate time is unfixed to measuring frequency principle, but the integral multiple in measured signal cycle, therefore with
Measured signal synchronizes, and is therefore also called multi-period synchronizing method.The method makes NxWith NsRising edge synch, eliminate tested letter
Number counting time produce ± 1 circular error, certainty of measurement is greatly improved, and achieves the equally accurate during whole measurement
Measure.During measuring, there are two enumerators respectively to standard-frequency signal Fs and tested frequency signal FxCount simultaneously.First
First providing preset gate rising edge and open signal, now two enumerators do not start counting up, and are intended to by the time be believed by measured frequency
Number rising edge arrive time, two enumerators the most really start counting up.Then when preset gate trailing edge shutdown signal arrives,
Two enumerators stop counting the most immediately, and are intended to until the rising edge of tested frequency signal arrives just stop counting, complete
Become one-shot measurement process.The frequency of bidding calibration signal is Fs, the frequency of measured signal is Fx, measuring time period Tws(unit lock
The door time) in the periodicity of tested frequency signal be Nx, the periodicity of standard-frequency signal is Ns, then have
The frequency that can be obtained measured signal relative datum signal by above formula is Nx/Ns, as shown in Figure 5.This relative frequency value
This value can be gone out in FPGA internal calculation can ensure that N by data bus transmission to CPUxAnd NsAbsolute synchronization, decrease by
Transport part synchronizes the error result brought, and meanwhile, the calculating speed of FPGA is far above CPU, shortens while reducing cpu load
Time of perfect measurement.(4) the relative frequency value in main control unit CPU part readable data bus, is multiplied by demarcation
After reference clock frequency value i.e. can get accurate measured signal absolute frequency value.Wherein, reference signal frequency value can be passed through
The 10MHz reference signal of correction FPGA output obtains.Meanwhile, CPU part can be collaborative by communication interface and remote terminal communication
Work, it is also possible to carry out man-machine interaction by the touch display screen of extension.In a preferred scheme, the waveform of frequency measurement module
Modulate circuit as shown in Figure 4, including in-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit, Schmidt trigger；Quilt
Survey signal through in-phase proportion amplifying circuit, in-phase proportion amplifier amplifies signals amplitude so that the conversion of rear class waveform can identify
Range of signal wider.Then pass through amplitude limiter circuit and the signal of 1～12V is limited in below 0.7V, then put through rear class filtering
After big, input Schmidt trigger is converted into square wave, and now signal amplitude scope meets the IO level input range of FPGA, now
Utilize equal precision measurement module can measure the frequency values of this signal.
Moving to left 32 is to utilize the calculating advantage of DSP in FPGA and minimizing to process the complicated fractional representation form of FPGA
And the operation carried out, NxExpand 232Times, fraction result has been saved in 64 bit data of integer part, writes data at FIFO
During can ensure to lose the data of any one passage, the most there is not NxAnd NsNonsynchronous situation, result is transferred to
Having only to move to right 32bit in ARM be multiplied by correction crystal oscillator frequency again and i.e. can get accurate result, the error that this algorithm brings is 2-32, negligible for measuring.Meanwhile, the result of controller calculates and has only to 32 shifting functions, greatly reduces CPU
Utilization rate.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For Yuan, under the premise without departing from the principles of the invention, it is also possible to make some improvements and modifications, these improvements and modifications also should
It is considered as protection scope of the present invention.Although additionally, employ some specific terms in this specification, but these terms are only
For convenience of explanation, the present invention is not constituted any restriction.
Claims (10)
1. a multi channel signals frequency measuring block based on SOC(system on a chip), it is characterised in that include SOC(system on a chip) main control
Device, described SOC(system on a chip) master controller connects power module, touch-control module and peripheral interface, described SOC(system on a chip) main control respectively
Device includes main control unit and the Auxiliary Control Element interconnected respectively and FPGA module with main control unit, and described FPGA module is even
Connecing frequency measurement module, described main control unit connects communication module, and described frequency measurement module has measured signal interface, described communication mould
Block remote terminal interface, described touch-control module has touch display screen interface.
Multi channel signals frequency measuring block based on SOC(system on a chip) the most according to claim 1, it is characterised in that described
Frequency measurement module includes in-phase proportion amplifying circuit that front-end circuit, described front-end circuit include being sequentially connected with, amplitude limiter circuit, filtering
Amplifying circuit and Schmidt trigger, described Schmidt trigger connects described FPGA module.
Multi channel signals frequency measuring block based on SOC(system on a chip) the most according to claim 1, it is characterised in that described
Including in-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit and Schmidt trigger in frequency measurement module, measured signal is first
Through in-phase proportion amplifying circuit, then pass through amplitude limiter circuit and the signal of 1～12V is limited in below 0.7V, then through rear class
Inputting Schmidt trigger after filter and amplification and be converted into square wave, now signal amplitude scope meets the IO level input model of FPGA
Enclose, now utilize equal precision measurement module to get final product the periodicity of units of measurement this signal gate time.
Multi channel signals frequency measuring block based on SOC(system on a chip) the most according to claim 1, it is characterised in that described
In-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit and Schmidt trigger, measured signal warp is included in frequency measurement module
Cross in-phase proportion amplifier amplifies signals amplitude so that the range of signal that the conversion of rear class waveform can identify is wider, then passes through limit
The signal of 1～12V is limited in below 0.7V by width circuit, then input Schmidt trigger is converted into after rear class filter and amplification
Square wave, now signal amplitude scope meets the IO level input range of FPGA, now utilizes equal precision measurement module to measure
The frequency values of this signal.
Multi channel signals frequency measuring block based on SOC(system on a chip) the most according to claim 1, it is characterised in that described
Frequency measurement module includes the first operational amplifier that front-end circuit, described front-end circuit include being sequentially connected with, signal clamping circuit, filter
Ripple inductance and the second operational amplifier, described second operational amplifier connects Schmidt trigger, and described Schmidt trigger is even
Connect described FPGA module.
Multi channel signals frequency measuring block based on SOC(system on a chip) the most according to claim 5, it is characterised in that described
One end of one end and limit frequency inductance that the first operational amplifier connects described signal clamping circuit by the first resistance is formed
Primary nodal point, described signal clamping circuit includes the first clamp diode and the second clamp diode, the first clamp diode
The anode of negative terminal and the second clamp diode is all connected with described primary nodal point, the anode of the first clamp diode and the second clamper two
The negative terminal of pole pipe is all connected with earth terminal, and the other end of described filter inductance connects described second operation amplifier by the second resistance
Device, and connect earth terminal by the 3rd resistance.
Multi channel signals frequency measuring block based on SOC(system on a chip) the most according to claim 1, it is characterised in that described
Main control unit and described Auxiliary Control Element constitute dual core processor, and described dual core processor interconnects on-chip bus respectively and connects
Mouth bus, described on-chip bus connects I/O unit by different external bus protocol respectively, and described interface bus is mutual
Being connected in programmed logical module, described programmed logical module includes field programmable gate array module, Digital Signal Processing mould
Block, system monitoring module, Peripheral Component Interconnect module and random access memory module, described system monitoring module and described peripheral hardware
Component interconnection module is provided with Serial Peripheral Interface (SPI).
Multi channel signals frequency measuring block based on SOC(system on a chip) the most according to claim 1, it is characterised in that described
Frequency measurement module is with array distribution, and each frequency measurement module all receives standard signal frequency and measured signal frequency, described frequency measurement mould
Block rate of connections computing divider, described frequency calculation divider utilizes and moves to left tested letter in the unit gate time after 32bit
Number periodicity is divided by with reference signal periodicity in unit gate time, obtains the measured signal relative to reference clock relative to frequency
Rate value, is uploaded to microprocessor or CPU to obtain definitely by this relative frequency value by ordered storage device and transmission channel interface
Frequency values.
Multi channel signals frequency measuring block based on SOC(system on a chip) the most according to claim 1, it is characterised in that described
Remote terminal interface connects remote terminal, and described multi channel signals frequency measuring block is assisted with remote terminal by the TCP of extension
With work.
Multi channel signals frequency measuring block based on SOC(system on a chip) the most according to claim 1, it is characterised in that institute
State touch display screen interface and connect touch display screen, to carry out man-machine interaction.
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