CN106324341B - A kind of multi channel signals frequency measuring block based on system on chip - Google Patents
A kind of multi channel signals frequency measuring block based on system on chip Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
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Abstract
A kind of multi channel signals frequency measuring block based on system on chip, system on chip, that is, the SoC chip or system level chip, the frequency measuring block is conducive to the precise measurement for realizing multi channel signals frequency on the area of very little by its high integration, it can also be cooperated by the TCP and remote terminal of extension, human-computer interaction is carried out by the touch display screen curtain of extension, it is characterized in that, including system on chip master controller, the system on chip master controller is separately connected power module, touch-control module and peripheral interface, the system on chip master controller includes main control unit and the Auxiliary Control Element interconnected respectively with main control unit and FPGA module, the FPGA module connects frequency measurement module, the main control unit connection communication module, the frequency measurement module has measured signal interface, the communication mould Block remote terminal interface, the touch-control module have touch display screen interface.
Description
Technical field
The present invention relates to instrument field, especially a kind of multi channel signals frequency measurement mould based on system on chip
Block, the system on chip, that is, SoC chip or system level chip, the frequency measuring block are conducive to through its high integration in very little
Area on realize the precise measurement of multi channel signals frequency, can also be cooperated, be led to by the TCP of extension and remote terminal
The touch display screen curtain for crossing extension carries out human-computer interaction.
Background technique
The high-acruracy survey of frequency can be such that people more effectively recognize, analyze signal, require low-power consumption, high-precision certain
The frequency measurement occasion of degree, XILINX series SoC can complete to more efficient the task, FPGA frequency can steady operation in 250M
More than, the frequency of TTL signal can be accurately measured using Equal-precision digital frequency measure method, cooperate ARM system in front-end circuit and piece,
The frequency measurement of achievable arbitrary signal and as the result is shown, transmission etc. functions.The nineties in last century, SoC (System on a
Chip, a kind of one chip that microprocessor, Analog IP core, digital IP kernel and memory etc. is integrated, also known as system on chip
Or system level chip) concept is suggested, SoC can effectively reduce electronics/information system product development cost, shorten exploitation week
Phase improves the competitiveness of product, its purpose is to overcome some difficulties encountered in multi-chip Integration System Design, shortens each
Delay time between device.With the continuous development of SoC technology and perfect, integrated processor, logic device and deposit on a single chip
Reservoir etc. can complete the functions such as the acquisition, processing and transmission of signal, improve the speed of system, reduce hardware configuration
Complexity and overall cost.Realize that the SOPC technology of SoC function has been able to mature insertion with the FPGA of programming device
Soft, hard nucleus management device IP has flexible design method, can cut, is scalable, having the function of software and hardware in-system programmable components
Energy.Meanwhile linux system can also be run in the FPGA processor of mainstream at present, writing for application program is facilitated, high collection is made
The frequency measuring block of Cheng Du becomes possibility.
Summary of the invention
The present invention is in view of the deficiencies in the prior art or insufficient, provides a kind of multi channel signals based on system on chip
Frequency measuring block, the system on chip, that is, SoC chip or system level chip, the frequency measuring block are conducive to through its height collection
Cheng Du realizes the precise measurement of multi channel signals frequency on the area of very little, can also pass through the TCP and remote terminal of extension
It cooperates, human-computer interaction is carried out by the touch display screen curtain of extension.
Technical scheme is as follows:
A kind of multi channel signals frequency measuring block based on system on chip, which is characterized in that including system on chip master control
Device processed, the system on chip master controller are separately connected power module, touch-control module and peripheral interface, the system on chip master control
Device processed includes main control unit and the Auxiliary Control Element interconnected respectively with main control unit and FPGA module, the FPGA module
Frequency measurement module, the main control unit connection communication module are connected, the frequency measurement module has measured signal interface, the communication
Module has remote terminal interface, and the touch-control module has touch display screen interface.
The frequency measurement module includes front-end circuit, the front-end circuit include sequentially connected in-phase proportion amplifying circuit,
Amplitude limiter circuit, filter amplification circuit and Schmitt trigger circuit, the Schmidt trigger connect the FPGA module.
It include in-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit and schmidt trigger in the frequency measurement module
Device, measured signal first pass through in-phase proportion amplifying circuit, then pass through amplitude limiter circuit by the signal of 1~12V be limited in 0.7V with
Under, Schmidt trigger is inputted after amplifying using rear class filtering and is converted into square wave, and signal amplitude range meets FPGA's at this time
IO level input range, at this time using equal precision measurement module can the measurement unit gate time signal periodicity.
It include in-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit and schmidt trigger in the frequency measurement module
In-phase proportion amplifier amplifies signals amplitude is passed through in device, measured signal, and the range of signal that rear class waveform convertion is identified is more
Width, then pass through amplitude limiter circuit the signal of 1~12V is limited in 0.7V hereinafter, after amplifying using rear class filtering input apply it is close
Special trigger is converted into square wave, and signal amplitude range meets the IO level input range of FPGA at this time, is surveyed at this time using equally accurate
Amount module is the frequency values that can measure the signal.
The frequency measurement module includes front-end circuit, and the front-end circuit includes sequentially connected first operational amplifier, letter
Number clamp circuit, filter inductance and second operational amplifier, the second operational amplifier connects Schmidt trigger, described to apply
Schmitt trigger connects the FPGA module.
First operational amplifier connects one end and the filter inductance of the signal clamping circuit by first resistor
One end is formed by first node, and the signal clamping circuit includes the first clamp diode and the second clamp diode, and first
The anode of the negative terminal of clamp diode and the second clamp diode is all connected with the first node, the anode of the first clamp diode
It is all connected with ground terminal with the negative terminal of the second clamp diode, the other end of the filter inductance connects described by second resistance
Two operational amplifiers, and ground terminal is connected by 3rd resistor.
The main control unit and the Auxiliary Control Element constitute dual core processor, and the dual core processor interconnects respectively
On-chip bus and interface bus, the on-chip bus connect I/O unit, institute by different external bus protocols respectively
It states interface bus and is interconnected to programmed logical module, the programmed logical module includes field programmable gate array module, number
Word signal processing module, system monitoring module, Peripheral Component Interconnect module and random access memory module, the system monitoring mould
Block and the Peripheral Component Interconnect module are provided with Serial Peripheral Interface (SPI).
For the frequency measurement module with array distribution, each frequency measurement module receives standard signal frequency and measured signal frequency
Rate, the frequency measurement module rate of connections operation divider, the frequency calculation divider utilize and move to left the unit gate after 32bit
Measured signal periodicity is divided by with reference signal periodicity in unit gate time in time, obtains the quilt relative to reference clock
Survey signal relative frequency value, by the relative frequency value by ordered storage device and transmission channel interface be uploaded to microprocessor or
CPU is to obtain absolute frequency value.
The remote terminal interface connects remote terminal, the TCP that the multi channel signals frequency measuring block passes through extension
It cooperates with remote terminal；The touch display screen interface connects touch display screen, to carry out human-computer interaction.
Technical effect of the invention is as follows: by the multi channel signals frequency measuring block, can monitor multi channel signals frequency
The accurate results of rate can also be cooperated by the TCP and remote terminal of extension, pass through the touch display screen curtain of extension
Carry out human-computer interaction.Relative frequency value on CPU readout data bus can be obtained multiplied by calibrated reference clock frequency value
Accurate measured signal absolute frequency value.CPU also has many peripheral interfaces, expansible other application.
Detailed description of the invention
Fig. 1 is to implement a kind of structural schematic diagram of the multi channel signals frequency measuring block based on system on chip of the present invention.
Fig. 2 is the front-end circuit schematic diagram in frequency measurement module.
Fig. 3 is system on chip SoC structural schematic diagram.SoC refers to systemonchip, System-on-a-Chip, on piece system
System.
Fig. 4 is Equal-precision digital frequency measure schematic illustration.
Fig. 5 is frequency measurement calculation process block diagram.
Appended drawing reference lists as follows: 1- multi channel signals frequency measuring block；2- power module；3- peripheral interface；4-
FPGA module/logic gate array/Field Programmable Gate Array (field programmable gate array module)；5- master
Control unit/Core1 (the first core in multi-core processor)；6- Auxiliary Control Element/Core2 (the second core in multi-core processor)；
7- system on chip master controller；8- frequency measurement module；9- communication module；10- touch-control module/other circuits；11- measured signal；12-
Remote terminal；13- touch display screen；14- frequency calculation divider/division IP kernel；FsStandard signal frequency；FxMeasured signal
Frequency；NxThe periodicity of tested frequency signal；NsThe periodicity of standard-frequency signal；TwsMeasuring section effective unit lock
The door time；TwaMeasuring section preset unit gate time；T- preset gate time；Ts-Practical gate time；RAM- is random
Access memory module/dual port RAM；FIFO- ordered storage device；AXI4_Lite- transmission channel interface/AXI4 interface communications protocol
Sub-protocol；ARM- microprocessor；PS- processor system belongs to microprocessor ARM, and PS is then mainly by APU
(Application Processor Unit, application processor unit), memory interface (Memory interfaces), IOP
(I/O peripherals, input/output peripheral) and center interconnection (Central interconnect) composition；AXI- interface is logical
Believe protocol/interface bus；AMBA- advanced microcontroller bus architecture, Advanced Microcontroller Bus
Architecture or on piece interconnection specification agreement or on-chip bus；PL- programmed logical module, such as FPGA；IO- is defeated
Enter/output unit；SPI- Serial Peripheral Interface (SPI), Serial Peripheral Interface；PCIe- bus interface module,
PCI-Express, PCI, Peripheral Component Interconnect module, Peripheral Component Interconnect；DSP- number letter
Number processing module, Digital Signal Process, dsp chip are the chip for referring to realize Digital Signal Processing；
SysMon- system monitoring module；Various external interface/the external bus protocols of CAN, UART, SDIO, USB, GigE-；U10- first
Operational amplifier；Test- second operational amplifier；The first clamp diode of D3-；The second clamp diode of D4-；74HC14- is applied
Schmitt trigger；L3- filter inductance；R3- first resistor；R42- second resistance；R43- 3rd resistor；GND- ground terminal.
Specific embodiment
With reference to the accompanying drawing (Fig. 1-Fig. 5) the present invention will be described.
Fig. 1 is to implement a kind of structural schematic diagram of the multi channel signals frequency measuring block based on system on chip of the present invention.
Fig. 2 is the front-end circuit theory structure schematic diagram in frequency measurement module.Fig. 3 is system on chip SoC structural schematic diagram.SoC, which refers to, is
System single-chip, System-on-a-Chip, chip system, system level chip, system on chip.Fig. 4 is Equal-precision digital frequency measure original
Manage schematic diagram.Fig. 5 is frequency measurement calculation process block diagram.As shown in Figures 1 to 5, a kind of multi-pass based on system on chip
Road signal frequency measurement module 1, including system on chip master controller 7, the system on chip master controller 7 are separately connected power supply mould
Block 2, touch-control module 10 and peripheral interface 3, the system on chip master controller 7 include main control unit 5 and respectively with main control
The Auxiliary Control Element 6 and FPGA module 4 that unit 5 interconnects, the FPGA module 4 connect frequency measurement module 8, the main control unit
5 connection communication modules 9, the frequency measurement module 8 have measured signal interface (for receiving measured signal 11), the communication module
9 have remote terminal interface (for connecting remote terminal 12), and the touch-control module 10 has touch display screen interface (for connecting
Connect touch display screen 13).The frequency measurement module 8 includes front-end circuit, and the front-end circuit includes sequentially connected in-phase proportion
Amplifying circuit (such as first operational amplifier U10), amplitude limiter circuit, filter amplification circuit (such as second operational amplifier Test)
With Schmidt trigger 74HC14, the Schmidt trigger connects the FPGA module 4.
It include voltage follower circuit, amplitude limiter circuit, filter amplification circuit and hysteresis comparator, quilt in the frequency measurement module 8
Survey signal and first pass through voltage follower circuit, then pass through amplitude limiter circuit the signal of 1~12V is limited in 0.7V hereinafter, using
Input Schmidt trigger 74HC14 is converted into square wave after rear class filtering amplification, and signal amplitude range meets the IO electricity of FPGA at this time
Flat input range, at this time using equal precision measurement module can the measurement unit gate time signal periodicity.Alternatively, described
It include in-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit and Schmidt trigger circuit, in-phase proportion in frequency measurement module
Amplifier amplifies signals amplitude, the range of signal that rear class waveform convertion is identified is wider, then pass through amplitude limiter circuit by 1~
The signal of 12V be limited in 0.7V hereinafter, after amplifying using rear class filtering input Schmidt trigger be converted into square wave, believe at this time
Number amplitude range meets the IO level input range of FPGA, is at this time that can measure the frequency of the signal using equal precision measurement module
Value.
The frequency measurement module 8 includes front-end circuit, and the front-end circuit includes sequentially connected first operational amplifier
U10, signal clamping circuit, filter inductance L3 and second operational amplifier Test, the second operational amplifier Test connection are applied
Schmitt trigger 74HC14, the Schmidt trigger 74HC14 connection FPGA module 4.First operational amplifier
U10 connects one end of the signal clamping circuit by first resistor R3 and one end of filter inductance L3 is formed by first segment
Point, the signal clamping circuit include the first clamp diode D3 and the second clamp diode D4, the first clamp diode D3's
The anode of negative terminal and the second clamp diode D4 are all connected with the first node, the anode of the first clamp diode D3 and the second pincers
The negative terminal of position diode D4 is all connected with ground terminal GND, and the other end of the filter inductance L3 passes through described in second resistance R42 connection
Second operational amplifier Test, and pass through 3rd resistor R43 connection ground terminal GND.The main control unit 5 and auxiliary control
Unit 6 processed constitutes dual core processor PS, and the dual core processor PS interconnects on-chip bus AMBA and interface bus AXI, institute respectively
On-chip bus AMBA is stated to connect by different external bus protocols (for example, SPI, CAN, UART, SDIO, USB, GigE etc.) respectively
I/O unit IO is met, the interface bus AXI is interconnected to programmed logical module PL, the programmed logical module PL
Including field programmable gate array module FPGA, digital signal processing module DSP, system monitoring module SysMon, external components
Interconnecting modules PCIe and random access memory module RAM, the system monitoring module SysMon and the Peripheral Component Interconnect mould
Block PCIe is provided with serial peripheral equipment interface SPI.
The frequency measurement module 8 receives standard signal frequency F with array distribution, each frequency measurement module 8sAnd measured signal
Frequency Fx, the 8 rate of connections operation divider 14 of frequency measurement module, the frequency calculation divider 14 is using after moving to left 32bit
Unit gate time in measured signal periodicity NxWith reference signal periodicity N in unit gate timesIt is divided by, obtains opposite
In the measured signal relative frequency value of reference clock, which is passed through into ordered storage device FIFO and transmission channel interface
AXI4_Lite is uploaded to microprocessor ARM or CPU to obtain absolute frequency value.The remote terminal interface connects remote terminal
12, the multi channel signals frequency measuring block 1 is cooperated by the TCP and remote terminal 12 of extension；The touch display
Shield interface and connect touch display screen 13, to carry out human-computer interaction.
The present invention provides a kind of high integration frequency measuring block based on SoC, comprising: master controller, front-end circuit,
Middle master controller includes main control unit, logic gate array, and main control unit can transmit and receive data between logic gate array,
Measured signal passes through frequency measurement module access logic gate array respectively, wherein the course of work of the system are as follows: a) front-end circuit will
FPGA is accessed after measured signal conditioning shaping；B) the measured signal periodicity that FPGA is measured moves to left 32, reference signal periodicity
The division IP in DSP is accessed, is as a result uploaded in CPU by data/address bus；C) CPU obtains this by reading device file and is tested
The frequency values of signal can also can be carried out man-machine by Xu in communication module to remote terminal by the touch display screen of extension
Interaction.Further, wherein the step a's) is implemented as follows, and measuring circuit includes that in-phase proportion is put in frequency measurement module
Big circuit, amplitude limiter circuit, filter amplification circuit, Schmidt trigger, measured signal first pass through in-phase proportion amplifying circuit, then
The signal of 1~12V is limited in 0.7V hereinafter, inputting Schmidt trigger after amplifying using rear class filtering by amplitude limiter circuit
It is converted into square wave, signal amplitude range meets the IO input range of FPGA at this time, can survey using equal precision measurement module at this time
Measure the periodicity of the unit gate time signal.Further, inside FPGA there is IP kernel to pass through tune in the b) step
Division IP is generated with DSP, measured signal periodicity and base in unit gate time in the unit gate time after 32bit will be moved to left
Calibration signal periodicity is divided by, and obtains the measured signal frequency relative to reference clock, which is passed through data/address bus
CPU is uploaded to obtain absolute frequency value.Further, the relative frequency value on CPU readout data bus, multiplied by calibrated
Accurate measured signal absolute frequency value can be obtained in reference clock frequency value.Wherein, reference signal frequency value can pass through correction
The 10M reference signal of FPGA output obtains.Further CPU can be communicated by communication interface with remote terminal, can also be passed through
The touch control display module of extension carries out human-computer interaction.Further, CPU also has many peripheral interfaces, expansible other application.
A kind of high integration frequency measuring block based on SoC, including SoC unit, frequency measurement principle, the frequency of optimization
Transmission principle, front-end circuit are calculated, the SoC unit is master controller, and the frequency measurement principle is Equal-precision digital frequency measure
Principle, the frequency of the optimization, which calculates transmission principle, can be reduced the utilization rate that CPU is reduced in the case where guaranteeing precision.Before described
Terminal circuit completion completion input signal is clamped, amplifies, the function of shaping.The wherein course of work of the system are as follows: front-end circuit
Input signal is amplified, is clamped, filter and amplification, inputs a signal into logic gate array after shaping, it is therefore an objective to by measuring signal
Conditioning is suitble to the Transistor-Transistor Logic level of measurement for suitable logic gate array；It is measured by the equally accurate frequency measurement module inside logic gate array
The periodicity of measured signal and the periodicity of reference signal, input after measured signal periodicity is moved to left 32bit in unit time
Division IP in DSP calculates the precise frequency value of measured signal, and is uploaded to main control unit；Main control unit can be read simultaneously
It shows each channel frequence value or frequency values is sent to remote terminal by interfaces such as networks.Front-end circuit in frequency measurement module
Including in-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit, Schmidt trigger；Measured signal first passes through compared with
Example amplifying circuit then passes through after the signal of 1~12V is limited in 0.7V hereinafter, amplifying using rear class filtering by amplitude limiter circuit
Input Schmidt trigger is converted into square wave, and signal amplitude range meets the IO level of programmable gate array (FPGA) at this time
Input range.The system also includes FPGA, DSP, CPU, FPGA mainly measures the week of measured signal in unit gate time
The periodicity of issue, reference signal, DSP mainly calculate the periodicity of measured signal, are then sent out frequency values by data/address bus
It send to CPU.The module includes communication module, a scalable network module, peripheral expansion module, touch display screen, main control list
First Core1 can be connect by communication module with remote terminal, can be interacted with the touching display screen in system；Auxiliary control is single
First Core2 can pass through peripheral expansion module and other peripheral circuit connections.
The present invention realizes the measurement of signal frequency in the case where guaranteeing degree of precision with lesser volume.One kind is based on
The high integration frequency measuring block of SoC, including master controller, front-end circuit.Master controller, that is, SoC (System on
AChip, microprocessor, Analog IP core, digital IP kernel and memory integrated one chip), complete the frequency at Transistor-Transistor Logic level signal
Rate measurement calculates, and the front-end circuit completion input signal is clamped, amplifies, the function of shaping.
Referring to Fig. 1, frequency measuring block of the present invention, including master controller, frequency measurement module, communication module, periphery are shown
Expansion module, expansible touch display screen curtain etc..Wherein, master controller includes main control unit Core1, Auxiliary Control Element
Core2, logic gate array FPGA, main control unit Core1 can be sent between Auxiliary Control Element Core2 and logic gate array
Receive data.And main control unit Core1 can be connect by communication module with remote terminal；Auxiliary Control Element Core2 can
By peripheral expansion module and other peripheral circuit connections, and can between the touch display screen of extension receiving and transmitting signal.It is tested
Signal accesses FPGA by front-end circuit.Measured signal is converted to the TTL within the scope of the IO input capability of FPGA by front-end circuit
Level；
By communication module, the result of calculating can be uploaded to remote terminal, and remote terminal can also be with main control unit
Core1, Auxiliary Control Element Core2, logic gate array FPGA are communicated, and gate time is adjusted, and show measurement result, are saved
The data acquired in real time are so as to later period readjustment, analysis data；Waveform conditioning circuit in frequency measurement module includes in-phase proportion amplification
Circuit, amplitude limiter circuit, filter amplification circuit, Schmidt trigger；Measured signal first passes through in-phase proportion amplifying circuit, passes through after
It crosses amplitude limiter circuit and the signal of 1~12V is limited in 0.7V hereinafter, inputting Schmidt trigger turn after amplifying using rear class filtering
Change square wave into, signal amplitude range meets the IO level input range of FPGA at this time.Utilize the equal precision measurement module in FPGA
It can measure and calculate measured signal frequency values.
Illustrate the course of work of the system below: (1) front-end circuit amplifies measured signal, clipping, filtering are put
Greatly, waveform is converted, and is adjusted to the Transistor-Transistor Logic level of the IO input range energy of FPGA, front-end circuit as shown in Fig. 2, U10 will be unknown
The signal of amplitude amplifies 10 times, and output peak signal is no more than the rail voltage of U10, by D1, D2 that signal is clamped to ± 0.7V
Signal impact when range, the presence of L3 can slacken booting significantly, Test by the signal of clipping amplify 3 times meet rear class apply it is close
The input reference signal of special trigger, Schmidt trigger can convert the signal into the standard for meeting FPGA input range
TTL signal.(2) system structure diagram of main control unit SoC is as shown in Fig. 3, and PS (ProcessorSystem) is the portion ARM
Point, the main amendment for completing measurement result resolves, control is realized, as the result is shown, the functions such as transmission, PL (Programmable
It Logic) is FPGA portion, the main frequency measurement and calculating for completing Transistor-Transistor Logic level.PS is then mainly by APU (Application
Processor Unit, application processor unit), memory interface (Memory interfaces), IOP (I/O
Peripherals, input/output peripheral) and center interconnection (Central interconnect) composition.(3) main control unit
FPGA portion obtains the periodicity of measured signal in unit gate time, base in unit gate time by equally accurate measuring frequency principle
The periodicity of calibration signal synchronizes to obtain the frequency values relative to reference signal by calling DSP to generate division IP kernel.Equally accurate
Measuring frequency principle is as shown in Fig. 4, its practical gate time is unfixed, but the integral multiple in measured signal period, therefore with
Measured signal is synchronous, therefore also known as multi-period synchronizing method.The method makes NxWith NsRising edge synch, eliminate to tested letter
± 1 circular error generating when number counting, measurement accuracy greatly improves, and realizes the equally accurate during entire measurement
Measurement.In measurement process, there are two counters respectively to standard-frequency signal Fs and tested frequency signal FxIt counts simultaneously.It is first
Preset gate rising edge open signal is first provided, two counters do not start counting at this time, but will be until being believed by measured frequency
Number rising edge arrive when, two counters just really start counting.Then when preset gate failing edge shutdown signal arrives,
Two counters do not stop counting immediately, but just to stop counting until the rising edge for being tested frequency signal arrives, complete
At one-shot measurement process.The frequency for being marked with calibration signal is Fs, the frequency of measured signal is Fx, in measuring section Tws(unit lock
Door the time) in be tested frequency signal periodicity be Nx, the periodicity of standard-frequency signal is Ns, then have
It is N by the frequency that above formula can obtain measured signal relative datum signalx/Ns, as shown in Fig. 5.The relative frequency value
Can be by data bus transmission to CPU, N can be guaranteed by going out the value in FPGA internal calculationxAnd NsAbsolute synchronization, reduce by
Transport part synchronizes bring error result, meanwhile, the calculating speed of FPGA is much higher than CPU, shortening while can be reduced cpu load
Time of complete measurement.(4) the relative frequency value in main control unit CPU part readable data bus, multiplied by calibration
Accurate measured signal absolute frequency value can be obtained in reference clock frequency value afterwards.Wherein, reference signal frequency value can pass through
The 10MHz reference signal of correction FPGA output obtains.Meanwhile CPU part can be communicated by communication interface with remote terminal, collaboration
Work can also carry out human-computer interaction by the touch display screen curtain of extension.In a preferred scheme, the waveform of frequency measurement module
Conditioning circuit is as shown in figure 4, include in-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit, Schmidt trigger；Quilt
It surveys signal and passes through in-phase proportion amplifying circuit, in-phase proportion amplifier amplifies signals amplitude enables rear class waveform convertion to identify
Range of signal it is wider.It then passes through amplitude limiter circuit and the signal of 1~12V is limited in 0.7V hereinafter, putting using rear class filtering
Input Schmidt trigger is converted into square wave after big, and signal amplitude range meets the IO level input range of FPGA at this time, at this time
It is the frequency values that can measure the signal using equal precision measurement module.
Moving to left 32 is to utilize the fractional representation form of the calculating advantage of DSP in FPGA and reduction processing FPGA complexity
And the operation carried out, NxExpand 232Times, fraction result has been saved in 64 data of integer part, and data are written in FIFO
It can guarantee the data that will not lose any one channel in the process, N be also not presentxAnd NsNonsynchronous situation, is as a result transferred to
Only need to move to right 32bit in ARM can be obtained accurate as a result, the algorithm bring error is 2 multiplied by amendment crystal oscillator frequency-32, can be neglected for measurement.Meanwhile the result of controller calculates and only needs 32 shifting functions, greatly reduces CPU
Utilization rate.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.In addition, although using some specific terms in this specification, these terms are only
For convenience of explanation, it does not limit the present invention in any way.
Claims (9)
1. a kind of multi channel signals frequency measuring block based on system on chip, which is characterized in that including system on chip main control
Device, the system on chip master controller are separately connected power module, touch-control module and peripheral interface, the system on chip main control
Device includes main control unit and the Auxiliary Control Element interconnected respectively with main control unit and field programmable gate array module, institute
State field programmable gate array module connection frequency measurement module, the main control unit connection communication module, the frequency measurement module tool
There is measured signal interface, the communication module has remote terminal interface, and the touch-control module has touch display screen interface；
The main control unit and the Auxiliary Control Element constitute dual core processor, and the dual core processor interconnects on piece respectively
Bus and interface bus, the on-chip bus connects I/O unit by different external bus protocols respectively, described to connect
For mouth bus interconnection in programmed logical module, the programmed logical module includes field programmable gate array module, number letter
Number processing module, system monitoring module, Peripheral Component Interconnect module and random access memory module, the system monitoring module and
The Peripheral Component Interconnect module is provided with Serial Peripheral Interface (SPI).
2. the multi channel signals frequency measuring block according to claim 1 based on system on chip, which is characterized in that described
Frequency measurement module includes front-end circuit, and the front-end circuit includes sequentially connected in-phase proportion amplifying circuit, amplitude limiter circuit, filtering
Amplifying circuit and Schmidt trigger, the Schmidt trigger connect the field programmable gate array module module.
3. the multi channel signals frequency measuring block according to claim 1 based on system on chip, which is characterized in that described
It include in-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit and Schmidt trigger in frequency measurement module, measured signal is first
By in-phase proportion amplifying circuit, amplitude limiter circuit is then passed through by the signal of 1~12V and is limited in 0.7V hereinafter, using rear class
Schmidt trigger is inputted after filter and amplification and is converted into square wave, and signal amplitude range meets field programmable gate array module at this time
IO level input range, at this time using equal precision measurement module can the measurement unit gate time signal periodicity.
4. the multi channel signals frequency measuring block according to claim 1 based on system on chip, which is characterized in that described
It include in-phase proportion amplifying circuit, amplitude limiter circuit, filter amplification circuit and Schmidt trigger, measured signal warp in frequency measurement module
In-phase proportion amplifier amplifies signals amplitude is crossed, the range of signal that rear class waveform convertion is identified is wider, then passes through limit
The signal of 1~12V is limited in 0.7V and is converted into hereinafter, inputting Schmidt trigger after amplifying using rear class filtering by width circuit
Square wave, signal amplitude range meets the IO level input range of field programmable gate array module at this time, utilizes equally accurate at this time
Measurement module is the frequency values that can measure the signal.
5. the multi channel signals frequency measuring block according to claim 1 based on system on chip, which is characterized in that described
Frequency measurement module includes front-end circuit, and the front-end circuit includes sequentially connected first operational amplifier, signal clamping circuit, filter
Wave inductance and second operational amplifier, the second operational amplifier connect Schmidt trigger, and the Schmidt trigger connects
Connect the field programmable gate array module module.
6. the multi channel signals frequency measuring block according to claim 5 based on system on chip, which is characterized in that described
First operational amplifier connects one end of the signal clamping circuit by first resistor and one end of filter inductance is formed by
First node, the signal clamping circuit include the first clamp diode and the second clamp diode, the first clamp diode
The anode of negative terminal and the second clamp diode is all connected with the first node, the anode of the first clamp diode and the second clamper two
The negative terminal of pole pipe is all connected with ground terminal, and the other end of the filter inductance connects second operation amplifier by second resistance
Device, and ground terminal is connected by 3rd resistor.
7. the multi channel signals frequency measuring block according to claim 1 based on system on chip, which is characterized in that described
For frequency measurement module with array distribution, each frequency measurement module receives standard signal frequency and measured signal frequency, the frequency measurement mould
Block rate of connections operation divider, the frequency calculation divider utilize tested letter in the unit gate time after moving to left 32bit
Number periodicity is divided by with reference signal periodicity in unit gate time, obtains the opposite frequency of measured signal relative to reference clock
The relative frequency value is uploaded to microprocessor or CPU by ordered storage device and transmission channel interface to obtain absolutely by rate value
Frequency values.
8. the multi channel signals frequency measuring block according to claim 1 based on system on chip, which is characterized in that described
Remote terminal interface connects remote terminal, and the multi channel signals frequency measuring block is assisted by the TCP and remote terminal of extension
With work.
9. the multi channel signals frequency measuring block according to claim 1 based on system on chip, which is characterized in that described
Touch display screen interface connects touch display screen, to carry out human-computer interaction.
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| CN107290588A (en) * | 2017-05-03 | 2017-10-24 | 芯海科技（深圳）股份有限公司 | A kind of system of high-precision multithreading measurement frequency |
| CN109062750A (en) * | 2018-09-13 | 2018-12-21 | 国家海洋环境预报中心 | A kind of high-performance computer test macro |
| CN111913038B (en) * | 2020-06-03 | 2023-12-19 | 大唐微电子技术有限公司 | Device and method for detecting frequency of multipath clock signals |
| CN111929607A (en) * | 2020-07-29 | 2020-11-13 | 湖北民族大学 | IP core for realizing real-time detection of multiphase power phase and power factor by utilizing FPGA |
| CN117971074B (en) * | 2024-04-01 | 2024-07-05 | 深圳贝特莱电子科技股份有限公司 | Main control system supporting touch and display, signal time sequence control method and electronic cigarette |
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