CN111913038B - Device and method for detecting frequency of multipath clock signals - Google Patents
Device and method for detecting frequency of multipath clock signals Download PDFInfo
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Abstract
The invention discloses a multi-channel clock signal frequency detection device, which comprises a control module, a clock switching module and a frequency detection module, wherein the control module is used for controlling the clock switching module to switch the clock signal frequency; the control module is configured to instruct the clock switching module to switch one of the multiple paths of clock signals to be detected in sequence according to preset detection configuration parameters, and store the received detection result as a detection result of the one path of clock signals; the clock switching module is configured to determine a path of clock signal to be detected from the multiple paths of clock signals according to the indication of the control module, and output the determined path of clock signal to the frequency detection module; the frequency detection module is used for detecting the frequency of the input clock signal and outputting a detection result to the control module. The invention also discloses a method for detecting the frequency of the multipath clock signal.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a device and a method for detecting frequency of multiple clock signals.
Background
The clock source of the chip is normal and stable, and plays a vital role in the chip work. Abnormality of the clock source of the chip may cause degradation of the chip performance and even may cause the chip to fail to operate properly. Meanwhile, in the technical field of chip security, many methods for measuring and calculating the characteristics of chip power consumption and the like through attack on a clock source realize attack on the chip. And is therefore very important for frequency detection of the clock source. In modern chip design, there are many clock sources depending on power consumption and application, so frequency detection is required for multiple clock sources.
In the existing frequency detection method, only one clock source is usually detected, and when multiple clock sources are detected, a plurality of frequency detection modules are used, and the principle is that each clock source is provided with one set of detection circuit, so that the number of circuits is increased, the area of a chip is increased, and the cost is increased.
How to effectively reduce the chip area and reduce the cost is also a problem to be solved in the field of multipath clock signal detection.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the invention provides a device and a method for detecting the frequency of a multi-path clock signal, which finish the dynamic polling detection of the multi-path clock through a frequency detection module and have the advantages of less circuit quantity, small circuit area and low cost.
The embodiment of the invention provides a multi-channel clock signal frequency detection device, which comprises,
the device comprises a control module, a clock switching module and a frequency detection module;
the control module is configured to instruct the clock switching module to switch one of the multiple paths of clock signals to be detected in sequence according to preset detection configuration parameters, and store the received detection result as a detection result of the one path of clock signals;
the clock switching module is configured to determine a path of clock signal to be detected from the multiple paths of clock signals according to the indication of the control module, and output the determined path of clock signal to the frequency detection module;
the frequency detection module is used for detecting the frequency of the input clock signal and outputting a detection result to the control module.
The embodiment of the invention also provides a method for detecting the frequency of the multipath clock signal, which comprises the steps of,
according to preset detection configuration parameters, sequentially indicating a clock switching module to switch one of the multiple paths of clock signals as a clock signal to be detected;
according to the indication of the control module, determining a path of clock signal to be detected from the accessed paths of clock signals, and outputting the path of clock signal to a frequency detection module;
and the frequency detection module is used for detecting the frequency of the input clock signal and outputting a detection result.
It can be seen that the embodiment of the invention realizes miniaturization and low cost of the multi-channel clock detection device by sharing one frequency detection module and respectively detecting the clock signals of a plurality of clock sources according to configuration in turn.
Drawings
Fig. 1 is a block diagram of a multi-channel clock frequency detection apparatus according to a first embodiment;
FIG. 2 is a flowchart illustrating operation of the control module according to the first embodiment;
FIG. 3 is a flowchart of a detection of a path clock signal in the first embodiment;
FIGS. 4a-4f are simulation diagrams of detection waveforms in the first embodiment;
fig. 5 is a block diagram of a multi-channel clock frequency detection apparatus according to a second embodiment;
fig. 6 is a flowchart of a method for detecting frequency of a multi-channel clock signal according to a third embodiment.
Detailed Description
The present invention will be described in further detail with reference to the drawings and the embodiments, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be arbitrarily combined with each other.
Example 1
This embodiment takes the detection of clock signals from the a-d four-way clock source shown in fig. 1 as an example.
An embodiment of the present invention provides a multi-channel clock signal frequency detection apparatus 10, whose structure is shown in fig. 1, including:
mainly comprises a control module 101, a clock switching module 102 and a frequency detection module 103.
The control module 101 is configured to realize a control function to the clock switching module 102 and the frequency detection module 103 and a processing and saving function to the detection result.
The clock switching module 102 is configured to implement a selective switching function of clock signals of respective clock sources.
The frequency detection module 103 is configured to perform frequency detection on the input clock and give an output detection result. The function of dynamically polling and detecting multiple clock sources by using one frequency detection module 103 is realized by the control module 102 and the clock switching module to complete the selection and switching of the detected clock sources.
Wherein, the control module 101 is configured to control the clock switching module 102 and the frequency detection module 103 according to preset detection configuration parameters; the detection configuration parameters at least comprise: the detection sequence and the detection time. For example, in this embodiment, polling detection is performed in the order of a, b, c, and d, and the detection interval time is 25 microseconds. Those skilled in the art can preset other parameters accordingly, for example, only detecting a part of clock signals, adjusting the detection sequence or the detection time, etc., which are not limited to the manner illustrated in the present embodiment.
Optionally, the multi-path clock signal frequency detection device further includes a self-checking function, the clock switching module 102 is also connected to the standard clock signal clk_selfcheck, and when the clock switching module 102 switches the standard clock signal and inputs the standard clock signal to the frequency detection module 103, the self-checking of the multi-path clock signal frequency detection device is performed.
The workflow of the control module 101 is shown in fig. 2, when normal detection or self-detection is started, all clock states are closed first, and each control signal is cleared, so that the purpose of this step is to ensure that when the detection state is soon re-entered after the abnormal exit detection, the last detected clock can be completely closed and then a new detection clock path is opened, so as to prevent the detected clock from being completely closed when the abnormal exit occurs, and the new detected path is opened and overlapped. After closing, starting to detect the CLKA clock path, if the detection is passed, jumping to a detection normal state, closing the CLKA clock path, detecting the frequency of the CLKB clock path according to similar steps, and carrying out polling detection on four paths of clocks in sequence. If the frequency of the A-path clock signal is detected to alarm, the corresponding abnormal detection state is entered, as shown in fig. 3. The other clock signals also adopt the similar flow of figure 3 if the abnormality occurs.
The self-checking process is used to check whether the frequency detection module 103 is normal, and the standard detected clock signal clk_selfcheck is input, and the checking process is similar to the checking process for normally checking other clock signals.
The control module 101 can realize the combination detection of all paths of clocks, can detect that 1 path of clocks are unequal to 4 paths of clocks, and can be expanded. The number of the clock paths is flexible and configurable, and the combination of the clock paths is flexible and configurable. Meanwhile, the device has a self-checking function, and normal detection and self-checking can be freely switched according to preset detection configuration parameters. The abnormal exit processing is performed, so that the normal operation can be ensured after the abnormal exit is detected again. And after an alarm occurs, the locking state is always kept under the condition that the system is not processed, so that the chip safety is ensured. That is, after an alarm occurs, if the detection device does not perform chip reset, the lock state will be maintained all the time.
The control module 101 latches the detection result at the same time, stops at the path to detect abnormal state when any path of clock frequency is abnormal, latches the detection result, and indicates the path of alarm to the system through the module output path of the device, and the high-frequency alarm or the low-frequency alarm is given. After latching, no polling detection is performed, the chip CPU is always kept in an alarm state, and the chip CPU stops running. Namely, the chip can not perform any operation under the abnormal condition, and the chip information is prevented from being obtained by attack detection. Even if the chip is in an abnormal state due to an abnormality caused by non-man-made attack, the chip should not continue to work. This function is a self-protection function after being attacked.
The device can restart normal detection after the system is reset, and restart normal polling detection if no abnormality exists.
The clock switching module 102 realizes the burr-free switching of each channel of clock, and because each clock frequency is different and is a different clock domain signal, the control signal given by the control module 101 is a system clock domain signal, and the control signal is synchronized to the clock domain of each clock channel and then is gated during switching, so that the burr-free switching is realized. The control signal sent by the control module 101 to the clock switching module 102 includes a signal indicating that the clock switching module 102 turns off the output of the clock signal currently being detected, or a signal indicating that the clock switching module 102 turns on the output of the new clock signal after switching.
When the clock switch 102 receives the signal for closing the output of the clock signal currently being detected, the clock switch synchronizes with the clock signal currently being detected, and then closes the output of the clock signal so as to realize the integrity of the waveform;
when the clock switch 102 receives the signal output by the new clock signal after switching on and switching off, the output of the clock signal is started again after synchronizing with the new clock signal after switching on, so as to realize the integrity of the waveform.
Optionally, the clock frequencies are different, and the synchronous time and the on/off time are different, so that the on/off of each clock is counted. After the clock path selected (after switching) is started, that is, after the control module 101 instructs the clock switching module 102 to start the signal output by the new clock signal after switching, the detection enable signal of the frequency detection module 103 is started after delay according to a preset start delay count, so that the detection is started; after waiting to completely close one clock, the control module 101 starts the other clock, that is, after instructing the switching module 102 to close the clock signal output currently being detected and delaying according to the preset closing delay count, instructs the switching module 102 to start the new clock signal output after switching, so that the new clock signal output starts. Therefore, no burrs are generated on the clocks, the clocks are not overlapped, and the accuracy of frequency detection is guaranteed.
The frequency detection module 103 performs reference timing by a standard count clock clk_reference. In the standard counting time, the detected clock signal clk_test is counted, and then the counting result is compared with a standard value, and the standard value is divided into a maximum value and a minimum value. And when the frequency is smaller than the minimum standard value, the frequency is considered to be lower, and when the frequency is larger than the maximum standard value, the frequency is considered to be higher, and the frequency is normal between the minimum standard value and the maximum standard value. The result is output to the control module 101 for registration processing.
The control module 101 instructs, through the clock switching control signal shown in fig. 1, the clock switching module 102 to select one of the multiple clock signals as a clock signal to be detected, that is, a new clock signal after switching; the frequency detection module is instructed to perform frequency detection by the enable control signal shown in fig. 1. The enable control signal is the detection enable signal, when the detection enable signal is turned on, the frequency detection module 103 performs frequency detection, and when the detection enable signal is turned off, the frequency detection module 103 does not perform frequency detection.
The clock switching module 102 is connected to the multi-path clock signal to be detected, optionally, is also connected to a standard clock signal for self-checking, and when one path of clock signal is switched from the connected multi-path clock signal as the clock signal to be detected according to the instruction of the control module 101, firstly, the output of the clock signal currently being detected is closed, and then a new path of clock signal is started as clk_test to be input into the frequency detection module.
In this embodiment, the simulation of the detection result is shown in fig. 4a, and a 4-channel clock source frequency simulation waveform diagram is detected. Wherein fd_en is a frequency detection module enable signal, and is turned on after each detected clock path is turned on. The clk_ref is a standard detection clock and always exists, the clk_flt clock is a self-detection clock clk_oscd8_fd and clk_trngaj_fd, clk_trngbj_fd, clk_trngcj_fd and clk_trngdj_fd, four paths of clocks which are detected are controlled and then enter the detection module, and therefore, the detection clocks in all paths are not overlapped and have no burrs. trng_fd_pass is a detection pass signal, it can be seen that after each detection is completed and the pass is made, trng_fd_err is an error indication signal, trng_fd_channel_err [3:0] is used to indicate which alarm is set, trng_fd_con [3:2] is used to indicate whether a high-frequency alarm or a low-frequency alarm (the set of signals are low-efficient and the other are not illustrated as high-efficient), and the detection shown in fig. 4a is normally not alarm.
In this embodiment, the timing waveform of the self-checking clock signal is shown in fig. 4 b; the waveform of the detection timing of the a-way signal CLKA is shown in fig. 4 c; a. xu Boxing when four paths of clock signals b, c and d are alternately detected is shown in fig. 4 d; detecting a time sequence waveform of an alarm of the b-path clock signal, as shown in fig. 4e, wherein trng_fd_con is the low-efficiency register, wherein [3] represents a low-frequency alarm, and [2] represents a high-frequency alarm; the waveform diagram of the alarm time sequence of the B-path clock signal CLKB is alternately detected, as shown in fig. 4f, wherein the B-path alarm signal always exists after the alarm is stopped, and the CPU is reset until the chip system is reset.
Example two
An embodiment of the present invention provides a multi-channel clock signal frequency detection apparatus 50, as shown in fig. 5, comprising,
a control module 501, a clock switching module 502 and a frequency detection module 503;
the control module 501 is configured to instruct the clock switching module to switch one of the multiple paths of clock signals in sequence to be a clock signal to be detected according to a preset detection configuration parameter, and store a received detection result as a detection result of the one path of clock signal;
the clock switching module 502 is configured to determine, according to the instruction of the control module, one clock signal to be detected from the multiple clock signals, and output the determined one clock signal to the frequency detection module;
the frequency detection module 503 is configured to perform frequency detection on the input one clock signal, and output a detection result to the control module 501.
Optionally, the control module 501 is further configured to instruct the clock switching module to close the output of the clock signal to the frequency detection module and instruct the frequency detection module to clear the detection result before sequentially instructing the clock switching module to switch one of the multiple clock signals to be the clock signal to be detected.
Optionally, the control module 501 instructs the clock switching module to switch one of the multiple clock signals to be a clock signal to be detected, including:
closing a detection enabling signal of the frequency detection module; instructing the clock switching module to close the output of the clock signal currently being detected;
instructing the clock switching module to start the output of the new clock signal after switching; and starting a detection enabling signal of the frequency detection module.
Optionally, the clock switching module 502 is further configured to close the output of the clock signal currently being detected after synchronizing with the clock domain of the clock signal currently being detected according to the received indication of closing the output of the clock signal currently being detected;
or,
the clock switching module 502 is further configured to start outputting the new clock signal after synchronizing with the clock domain of the new clock signal according to the received indication of outputting the new clock signal after switching on.
Optionally, the control module 501 instructs the clock switching module to start outputting of the new clock signal after switching; turning on a detection enabling signal of the frequency detection module, including:
after the clock switching module 502 is instructed to start the output of the switched new clock signal, the detection enabling signal of the frequency detection module is started after the output is delayed according to the start delay count corresponding to the new clock signal;
or,
the control module 501 instructs the clock switching module 502 to turn off the output of the clock signal currently being detected; instructing the clock switching module 502 to turn on the output of the switched new clock signal includes:
after instructing the clock switching module 502 to close the output of the clock signal currently being detected, after delaying according to the closing delay count corresponding to the current clock signal, instructing the clock switching module 502 to open the output of the new clock signal after switching.
Optionally, the control module 501 is further configured to latch the detection result and output alarm information when the processing result indicates that there is an abnormality after receiving the detection result and processing the detection result according to a preset rule.
Optionally, the control module 501 is further configured to instruct the clock switching module to switch the standard clock signal input to the clock switching module as the clock signal to be detected.
The preset detection configuration parameters at least comprise: the detection sequence and the detection time.
Example III
The embodiment of the invention provides a method for detecting the frequency of a multipath clock signal, which is shown in fig. 6, and comprises the following steps,
step 601, sequentially instructing a clock switching module to switch one of the multiple paths of clock signals to be the clock signal to be detected according to a preset detection configuration parameter;
step 602, according to the instruction of the control module, determining a path of clock signal to be detected from the multiple paths of clock signals to output to a frequency detection module;
in step 603, the frequency detection module performs frequency detection on the input one path of clock signal, and outputs a detection result.
Optionally, before step 601, the method further includes, before sequentially indicating that one clock signal to be detected is selected, step 600, indicating to turn off the output of the clock signal to the frequency detection module, and indicating the frequency detection module to clear the detection result.
Optionally, in step 602, determining a channel of clock signal to be detected from the multiple channels of accessed clock signals, and outputting the determined channel of clock signal to a frequency detection module, where the determining step includes:
and according to the received indication, determining one path of clock signal to be detected from the multiple paths of accessed clock signals, and starting the determined clock signal to output to the frequency detection module after synchronizing with the clock domain of the determined clock signal.
Optionally, in step 601, the instructing the clock switching module to switch one of the multiple clock signals to be a clock signal to be detected includes:
closing a detection enabling signal of the frequency detection module; instructing the clock switching module to close the output of the clock signal currently being detected;
instructing the clock switching module to start the output of the new clock signal after switching; and starting a detection enabling signal of the frequency detection module.
Optionally, the step 602 includes: according to the received indication of closing the output of the clock signal currently being detected, after synchronizing with the clock domain of the clock signal currently being detected, closing the output of the clock signal currently being detected;
or,
the step 602 includes: and starting the output of the new clock signal after synchronizing with the clock domain of the new clock signal according to the received indication of starting the output of the new clock signal after switching.
Optionally, the step 601 instructs the clock switching module to start outputting the new clock signal after switching; turning on a detection enabling signal of the frequency detection module, including:
after the clock switching module is instructed to start the output of the switched new clock signal, the detection enabling signal of the frequency detection module is started after the output is delayed according to the start delay count corresponding to the new clock signal;
or,
the step 601 indicates that the clock switching module turns off the output of the clock signal currently being detected; instructing the clock switching module to turn on the output of the switched new clock signal includes:
after the clock switching module is instructed to close the output of the clock signal which is currently being detected, the clock switching module is instructed to start the output of the new clock signal after switching after delaying according to the closing delay count corresponding to the current clock signal.
Optionally, the method further includes, after receiving the detection result and processing according to a preset rule, step 604, when the processing result indicates that there is an abnormality, latching the detection result, and outputting alarm information.
Optionally, the method further comprises instructing the clock switching module to switch the standard clock signal input to the clock switching module as the clock signal to be detected.
Optionally, the preset detection configuration parameters at least include: the detection sequence and the detection time.
It can be seen that the scheme provided by the embodiment of the invention realizes the dynamic polling detection of the multipath clocks by one frequency detection module, and has the advantages of small circuit quantity, small circuit area, low cost and low power consumption. Meanwhile, the number of the detectable clock sources is flexible and configurable, and the paths of the detectable clock sources are flexible and configurable (which paths are detected). Whether the function of the frequency detection module is normal or not can be detected, namely, the self-checking function of the frequency detection module can be realized, and the normal detection and the self-checking can be switched freely. The abnormal exit processing is carried out, so that the normal operation can be ensured after the abnormal exit is detected again. And outputting an alarm state after the alarm appears, indicating which way of alarm is the high-frequency alarm or the low-frequency alarm, and keeping the locking state all the time under the condition that the system does not process, so as to ensure the safety of the chip.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Claims (7)
1. A multi-channel clock signal frequency detection device is characterized by comprising,
the device comprises a control module, a clock switching module and a frequency detection module;
the control module is configured to instruct the clock switching module to switch one of the multiple paths of clock signals to be detected in sequence according to preset detection configuration parameters, and store the received detection result as a detection result of the one path of clock signals;
the clock switching module is configured to determine a path of clock signal to be detected from the multiple paths of clock signals according to the indication of the control module, and output the determined path of clock signal to the frequency detection module;
the frequency detection module is used for detecting the frequency of the input clock signal and outputting a detection result to the control module;
the control module instructs the clock switching module to switch one of the multiple clock signals to be a clock signal to be detected, and the method includes: closing a detection enabling signal of the frequency detection module; instructing the clock switching module to close the output of the clock signal currently being detected; instructing the clock switching module to start the output of the new clock signal after switching; starting a detection enabling signal of the frequency detection module;
the clock switching module is further configured to close the output of the clock signal currently being detected after synchronizing with the clock domain of the clock signal currently being detected according to the received indication of closing the output of the clock signal currently being detected; or the clock switching module is further configured to start the output of the new clock signal after synchronizing with the clock domain of the new clock signal according to the received indication of starting the output of the new clock signal after switching.
2. The apparatus of claim 1, wherein the device comprises a plurality of sensors,
the control module is further configured to instruct the clock switching module to close the output of the clock signal to the frequency detection module and instruct the frequency detection module to empty the detection result before sequentially instructing the clock switching module to switch one of the multiple clock signals to be the clock signal to be detected.
3. The apparatus of claim 1, wherein the device comprises a plurality of sensors,
the control module instructs the clock switching module to start the output of the new clock signal after switching; turning on a detection enabling signal of the frequency detection module, including:
after the clock switching module is instructed to start the output of the switched new clock signal, the detection enabling signal of the frequency detection module is started after the output is delayed according to the start delay count corresponding to the new clock signal;
or,
the control module instructs the clock switching module to close the output of the clock signal currently being detected; instructing the clock switching module to turn on the output of the switched new clock signal includes:
after the clock switching module is instructed to close the output of the clock signal which is currently being detected, the clock switching module is instructed to start the output of the new clock signal after switching after delaying according to the closing delay count corresponding to the current clock signal.
4. The device according to any one of claim 1 to 3, wherein,
the control module is further configured to latch the detection result and output alarm information when the processing result indicates that the abnormality exists after receiving the detection result and processing the detection result according to a preset rule.
5. The device according to any one of claim 1 to 3, wherein,
the control module is further configured to instruct the clock switching module to switch the standard clock signal input to the clock switching module as the clock signal to be detected.
6. The device according to any one of claim 1 to 3, wherein,
the preset detection configuration parameters at least comprise: the detection sequence and the detection time.
7. A method for detecting the frequency of a multipath clock signal is characterized by comprising the steps of,
according to preset detection configuration parameters, sequentially indicating a clock switching module to switch one of the multiple paths of clock signals as a clock signal to be detected;
according to the indication of the control module, determining a path of clock signal to be detected from the accessed paths of clock signals, and outputting the path of clock signal to the frequency detection module;
the frequency detection module is used for detecting the frequency of the input clock signal and outputting a detection result;
the indicating clock switching module switches one of the multiple paths of clock signals to be the clock signal to be detected, and the indicating clock switching module comprises: closing a detection enabling signal of the frequency detection module; instructing the clock switching module to close the output of the clock signal currently being detected; instructing the clock switching module to start the output of the new clock signal after switching; starting a detection enabling signal of the frequency detection module;
the clock switching module is used for closing the output of the clock signal currently being detected after synchronizing with the clock domain of the clock signal currently being detected according to the received indication of closing the output of the clock signal currently being detected; or the clock switching module starts the output of the new clock signal after synchronizing with the clock domain of the new clock signal according to the received instruction of starting the output of the new clock signal after switching.
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