JP2000286685A - Digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a digital filter which can have a high noise eliminating ability regardless of its filter constant. SOLUTION: A dissidence detector is composed of ExOR gates G1 and G2, an AND gate G3, an OR gate G4, and a D flip-flop FF3 and is operated for detecting noise with a sample clock SCLK having a frequency higher than that of a filter clock FCLK. When the detector detects noise, the detector prevents the output of a flip-flop FF1 from being inputted to another flip-flop FF2 by switching and controlling a selector S. The flip-flops FF1 and FF2 which are cascade-connected in two stages are operated by the filter clock FCLK and, unless the dissidence detector detects noise, the flip flop FF1 holds/ outputs input signals (a) at a certain sampling time of the clock FCLK. Then the flip-flop FF2 outputs the signals (a) as post-filter input signals at the next sampling time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a filter circuit, and more particularly to a digital filter.

[0002]

2. Description of the Related Art Conventionally, there has been known a filter circuit for filtering an input signal in order to prevent noise contained in the input signal from being taken into the inside thereof. Filter circuits have been proposed.

In a digital filter circuit of a filter circuit, for example, an input data value is sampled twice, and when the first and second values match, the value is taken in as an input after filtering. There is a digital filter circuit of a system (double reading collation system / two-stage sampling system; a kind of low-pass filter).

FIG. 8 is a diagram showing an example of the configuration of a conventional digital filter circuit. The digital filter circuit shown in the figure has a two-stage D flip-flop FF11,
The circuit includes an FF 12, an exclusive OR gate (hereinafter, referred to as an ExOR gate) G11, and a selector S.

An input signal a is input to a D terminal of a first-stage D flip-flop FF11, and a filter clock FCL is input.
The input signal a is output (held / output) from the Q terminal of the FF 11 at the rise of K (sampling clock). The output of the FF 11 is input to the selector S, and when the selector S is switched to “S = 1”,
The output of 11 becomes the input of FF12. Switching of the selector S is controlled by the output of the ExOR gate G11.
The ExOR gate G11 has an input signal and an output signal (FF)
12) are output, and if the values of the two do not match, “1” is output, and if the values of both match, “0” is output. The selector S is an ExOR gate G1
When the output of "1" is "1", it is switched to the "S = 1" side, and when it is "0", it is switched to the "S = 0" side.

Accordingly, the second stage D flip-flop F
When the selector S is at "S = 1", F12
When the output of F11 is input and the selector S is at "S = 0", the output of itself ("FF12") is input.

In such a configuration, for example, when a normal input signal (passband signal) as shown on the left side of FIG. 9 is input, when this signal is sampled twice, the first and second values are obtained. Since they match, this is output from the second-stage FF 12 as an output signal after filtering. Specifically, first, when the input signal changes from '0' to '1', the output signal is '0', so that the two input values to the ExOR gate G11 do not match, and the selector S
Is switched to the “S = 1” side. Then, at the first sampling timing (rising of the filter clock FCLK) after the change of the input signal, the FF 11 holds / outputs the input signal “1”, and the selector S is switched to “S = 1”. , The output '1' of the FF11 is
It is applied to twelve input terminals Dn. Then, as shown on the left side of FIG. 9, when the input signal is “1” also at the time of the second sampling, the FF 12 holds / outputs “1” which is the output of the FF 11. That is, the output signal changes from '0' to '1' at the second sampling timing after the change of the input signal.

On the other hand, although not shown in the figure, F1 is generated at the first sampling timing by chance coincident with the sampling period of "1" of the input signal a due to high frequency noise or the like.
F11 may hold / output “1”. Even in such a case, the input signal a returns to '0' before the second sampling timing (usually, the filter constant is
It is set so that “1” due to such high-frequency noise is not sampled twice in a row). At this time, the two input values to the ExOR gate G11 match, and the selector S sets “S = 0 ”side,
The input of the FF 12 is its own output. Therefore, at the second sampling timing, the FF 12 is held /
Since the output becomes its own current output state '0', a change in the input signal due to noise is not reflected on the output signal. That is, noise can be removed.

Although not particularly shown, in addition to the double reading collation method, a filter circuit in which a counter and a setting register are combined is operated by a filter clock so that the value of the input signal is maintained for a predetermined period. (Counter UP
There is also known a filter circuit in which the value is taken as an input after filtering when the value does not change. In this counter memory type filter circuit, the frequency of the filter clock FCLK is fixed,
Instead, the setting content of the count value can be changed, so that the filter constant can be changed. For example, if the set number of sampling continuations is “5”, if there is the same input value five times at the rising edge of FCLK, this is output as a filtered signal. In this case, the filter constant is [5 × 1 / F
CLK (time)].

In this method (counter method), when noise is detected, the count value is reloaded and counting is started from the beginning (UP-RESET mode), and the count value is decremented by -1 (decrement). There is a mode in which counting is continued (UP-DOWN mode). In any of the modes, when the count value reaches a specified number, the value of the input signal is taken in as an input value after filtering. In either method, the filter can be operated by selecting one frequency or one frequency from a plurality of filtering clocks.

[0011]

In the above-described conventional digital filter circuit, first, in a double read collation type filter circuit as shown in FIG. 8, a short width due to noise (width equal to or less than a clock cycle of a filter clock). Even if the '1' signal is inputted, it is not taken in internally, but it is accidentally inputted continuously in a form synchronized with the filter clock (as shown on the right side of FIG. 9). Situation), there is a possibility of being erroneously input as an input value. That is, for example, as shown on the right side of FIG. 9, when the “1” input signals due to the high-frequency noise are continuous and both of them are accidentally synchronized with the sampling period, the sampling value of the first-stage flip-flop FF11 is used. Becomes "1" twice consecutively, and this is reflected in the output of the flip-flop FF12 of the second stage. That is, noise cannot be removed. In other words, detecting an input change in an input signal, such as a portion surrounded by a circle (ellipse) indicated by a dotted line in the figure, leads to detection (removal) of noise. If the width of the input change is smaller than the clock cycle of the filter clock, there is a possibility that the '0' portion cannot be detected (no noise can be detected).

On the other hand, conventionally, there is known a method of using a high frequency clock as a filter clock in a circuit in which the above-described counter and register are combined.

However, this method has a problem that the circuit scale (particularly the counter) increases almost in proportion to the ratio between the cycle time of the filter clock and the filter time constant.

A method has been conventionally known in which an analog filter (usually a CR filter) having a time constant that blocks a pulse component having a width equal to or less than the filter clock cycle is provided in a stage preceding the digital filter.

In this method, the time constant of the analog filter is adjusted to the filter clock cycle. If it is necessary to increase the filter constant, the cycle of the filter clock must be increased (the frequency must be reduced).

When the filter constant increases, the sampling interval, that is, the reciprocal of the filter clock frequency, increases in proportion to the filter constant. Therefore, the width of the noise pulse taken in also increases in proportion. There was a problem that it would.

Further, as described above, the width of the noise pulse taken in becomes larger in proportion to the filter constant.
When the filter constant is selectable (variable), there has been a problem that the element constant of the analog filter must also be variable or adjusted to the maximum value.

On the other hand, if the digital filter at the subsequent stage is a circuit combining the above counter and setting register, the sensitivity of the digital filter itself is increased by increasing the number of bits of the counter, and the filter clock is fixed. Therefore, there is also a method of fixing the time constant of the analog filter.

However, in this method, if the frequency of the filter clock is not high to some extent, the element constant of the analog filter increases, the CR used increases, and the circuit scale (current consumption, mounting area, etc.) increases.
On the other hand, if the frequency of the filter clock is increased, the number of bits of the counter must be very large (for a desired filter constant), and this also leads to an increase in circuit size. .

An object of the present invention is to provide a digital filter capable of increasing the noise removing capability, further increasing the noise removing capability without increasing the circuit scale, and keeping the noise removing capability constant irrespective of the filter constant. It is to be.

[0021]

SUMMARY OF THE INVENTION A first digital filter according to the present invention comprises first and second cascaded filters operated by a filter clock corresponding to a filter constant.
A digital filter for filtering an input signal by a two-stage sampling method, wherein when a noise component included in the input signal is detected by a noise detection clock having a higher frequency than the filter clock, the second register And a noise detecting / controlling means for suppressing the update of the output.

For example, the first digital filter has a selector for inputting either the output of the first register or the output of the second register to the second register, and the noise detection / control means. When detecting that the output of the first register and the input signal do not match when the output of the first register and the output of the second register do not match, the first The selector is switched and controlled so that the output of the register is not input to the second register.

According to the first digital filter,
In a two-stage sampling digital filter,
By providing noise detection / control means for detecting noise using a noise monitoring clock having a higher frequency than the filter clock, the noise removal capability can be increased without depending on the filter constant.

Also, for example, the filter clock is:
It is generated at an arbitrary frequency division ratio based on the noise monitoring clock. Alternatively, the filter clock is generated as a clock having an arbitrary frequency based on the noise monitoring clock.

Even when such a filter clock frequency can be selected, the first digital filter corresponds to an arbitrary filter constant and has a constant noise removal capability (depending on the frequency of the noise monitoring clock). It can be.

Further, when the filter clock frequency can be selected, an analog filter is provided outside the digital filter (generally known).
According to the first digital filter,
The element constant of this analog filter can be reduced and can be common regardless of the filter constant.

A second digital filter according to the present invention has first and second cascaded registers operated by a filter clock corresponding to a filter constant, and filters an input signal by a counter method. A noise detection / control unit that operates with a noise detection clock having a higher frequency than the filter clock and suppresses updating of the output of the second register when noise included in the input signal is detected.

The counter method is a counter method in the UP-RESET mode or a counter method in the UP-DOWN mode. When the noise detection / control means detects noise, the counter method in the UP-RESET mode is The set value is reloaded into the counter, and the counter is decremented in the UP-DOWN mode counter method.

In the conventional counter method, the noise removal capability can be increased by increasing the frequency of the filter clock, but the circuit scale increases. According to the second digital filter described above, the noise removal capability can be increased by the noise detection / control means operated by the noise detection clock, so that the circuit scale does not increase.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a configuration diagram of a digital filter circuit 10 according to the first embodiment. The circuit 1 shown in FIG.
0 is divided into a twice-reading filter circuit (broken line portion A) and a filter clock differentiating circuit (broken-line portion B) when there are a plurality of (n) input signals. The circuits indicated by the broken lines A are required for the number of bits (n) (however, each D-flip-flop FF1, FF2, F
This is because F3 only needs to have one input / output having n input / outputs (Dn, Qn) and one filter clock differentiating circuit.

In FIG. 1, an input signal a input to, for example, an I / O device or the like is input to a first-stage D-flip-flop FF1 of two cascade-connected registers (FF1 and FF2). It is output from the second stage D-flip-flop FF2 as an input signal (output signal b). These two-stage registers (FF1, FF
2) operates by the filter clock FCLK.

A selector S is provided between the two-stage registers (FF1, FF2). The selector S is
When the input signal a is normal, it is switched to the “S = 0” side, and the output c of the FF1 is the input d of the FF2. Then, “mismatch detection” is performed by a mismatch detector described later.
When (noise detection) is performed, the FF 2 is switched to the “S = 1” side, and the FF 2 inputs its own output b in a loop.

The mismatch detector includes a D-flip-flop FF3, two ExOR gates G1, G2 and AN.
It is composed of a D gate G3 and an OR gate G4 (in the figure,
Indicated by a dashed line). The mismatch detector detects the first-stage register (FF) during a period in which the holding / output values of the first-stage and second-stage registers (FF1, FF2) are mismatched (b ≠ c).
When it is detected that the input to 1), that is, the input signal a and the output c of the FF 1 do not match (a ≠ c), the selector S is switched and controlled. In other words, the mismatch detector
When the output value c of the FF1 has changed due to noise or the like, this circuit detects the change and prevents the output of the FF1 from being reflected on the output of the FF2. Further, the mismatch detector is a circuit that operates with the sample clock SCLK (a noise monitoring clock having a higher frequency than the filter clock FCLK), and is independent of the filter constant (without depending on the frequency of the filter clock FCLK).
It allows to remove noise at high frequencies.

Hereinafter, the operation of the mismatch detector will be described in more detail. The output c of FF1 and the output b of FF2 are input to the ExOR gate G1. The ExOR gate G1 is configured to detect whether or not the output values of the first-stage and second-stage registers (FF1, 2) do not match (b） c) (output “1” if they do not match). . ExOR
The output c of the FF1 and the input signal a are input to the gate G2. The outputs of the two ExOR gates G1 and G2 are A
Input to ND gate G3.

The ExOR gates G1, G2 and AND
In the configuration including the gate G3, a period during which the output values of FF1 and FF2 do not match (b ≠ c), that is, at the time of the first sampling (the rising edge of FCLK) after the value of the input signal a changes, at the time of the second sampling Until Ex
The OR gate G1 outputs "1". If the input and output of the FF1 do not match (a @ c) during this time, the ExOR gate G2 also outputs "1", and AND
The output e of the gate G3 becomes '1'.

The configuration composed of the OR gates G4 and FF3 corresponds to the above-mentioned ExOR gates G1, G2 and AND gate G.
The sample clear signal SC generated / output by the filter clock differentiating circuit (D-flip-flop FF4 and NAND gate 10) at the next rising edge of the filter clock FCLK,
This is a configuration for holding the data until it is cleared by the LR.

By the operation of the above-described mismatch detector, the selector S determines whether or not a mismatch has been detected (noise detection).
By the output f (= 1) of F3, it is switched to "S = 1" until the next rise of the filter clock FCLK. Thus, the FF 2 receives its own output b as an input (maintains the current output value). In this way, for example, even if high-frequency noise enters twice in succession and both times happen to be synchronized with the rise of the filter clock FCLK, the output b of the FF2 maintains the current value without being affected by this. As a result, even if there is a noise pulse shorter than the cycle of FCLK,
Can be removed if the width is greater than the cycle of
The noise removal ability is improved.

An example of a specific operation of the filter circuit having the configuration shown in FIG. 1 will be described below with reference to FIG. In the example shown in FIG. 2, each rising edge of FCLK is set to t1 to t6, and the input signal a is originally a correct signal that changes from "0" to "1" slightly before the time point of t4. It is assumed that a short '1' signal due to high frequency noise has entered at each of the points t and t3.

With such an input signal a, the conventional circuit described above reads "1" twice at the rising edge of FCLK at t2 and t3, so that the output value after filtering at time t3 is "1". It will be 1 '. That is, noise is taken in. In other words, in the conventional circuit, when an input change (a change in which noise can be recognized) at a position indicated by a dotted circle (ellipse) on the figure is shorter than the period of FCLK, This could not be detected.

On the other hand, in the circuit of FIG. 1, first, at the rising edge (t2) of FCLK, the FF1 reads "1" of the first noise and outputs "1". The output c of FF1 becomes the input d of FF2.

Since the output b of FF2 is "0" until the next rising edge of FCLK (t3), the output c of FF1 does not match the output b of FF2, and the EXOR gate G1 outputs "1". Will be. In this state, if there is an input change indicated by a dotted circle (ellipse) in FIG. 2 (when the value of the input signal a becomes “0”), the input a of the FF1 is changed.
('0') does not match the output c ('1'),
The output of the ExOR gate G2 also becomes "1",
The output e of the ND gate G3 becomes '1', which is input to the FF3 via the OR gate G4. The FF 3 operates with the sample clock SCLK, and holds / outputs this input value “1” at the rise of SCLK after the input becomes “1” as described above. That is, as shown in FIG. 2, the value of the output f of the FF3 changes to “1”. At this time,
Since the selector S is switched to "S = 1" in accordance with the output change of the FF3, the input value of the FF2 changes from the state of "1" to its own output value of "0" as shown in FIG.

As a result, at the next rising edge of FCLK (t3), FF2 takes in its own output value "0", so that the output "1" of FF1 due to the noise becomes the output signal b.
(Ie, no noise is taken inside).

At this time, the FF3 is cleared by the sample clear signal SCLR generated as shown in FIG. 2 by the operation of the filter clock differentiating circuit described above. As a result, the output f becomes '0' and the selector S
Is switched to the “S = 0” side, so that the output c of FF1 again becomes the input d of FF2, and as shown in FIG.
The input d of 2 is '1'.

The input change (portion surrounded by a dotted line) that cannot be detected by FCLK between the sampling timings t3 and t4 is also detected by the above-described inconsistency detector operated by SCLK.
Becomes "1", and the selector S is switched to the "S = 1" side. Therefore, as shown in FIG. 2, the input d of the FF2 changes to its own output value '0', so that the next FCLK
Does not reflect the output '1' of the FF1 due to noise in the output signal b at the rising edge (t4) (that is, no noise is taken in).

As described above, according to the filter circuit of the first embodiment, especially in the filter circuit of the double read collation method, the conventional circuit cannot detect an input change having a width shorter than the cycle of the filter clock FCLK (noise change). But the filter clock FCL
By detecting this by a mismatch detector which operates with the sample clock SCLK which is a detection clock having a frequency higher than K, noise is not erroneously taken in. The noise removal capability is independent of the frequency of the filter clock FCLK, and the sample clock SCLK
Can be made constant by the frequency of

As shown in FIG. 2, when the input signal becomes "1" as a normal form, FF1 holds this at the rising edge (t4) of the filter clock FCLK.
Output and the output c of FF1 becomes the input d of FF2.
('1'). Then, in this state, the next FC
Since LK rises (t5), FF
The value “1” of the input d of 2 is held / output by the FF 2, and the output signal b becomes “1”.

According to the digital filter circuit 10 according to the first embodiment, in the configuration in which the frequency of the filter clock FCLK can be selected (variable filter constant) as described below, the noise removing capability is further improved. The effect will be obtained. This will be described in detail below with reference to FIG.

FIG. 3 is a diagram showing an example of a configuration enabling a plurality of filter constants to be set in the filter circuit of FIG.
FIG. 3A shows that the filter constant (1 / f (f; frequency)) of the filter clock FCLK is converted to the source frequency (SCL).
A configuration that allows selection from 2 ⁿ (2 ⁿ ) of K) will be described.

The right side of the figure shows the filter circuit 10 of FIG. As the sample clock SCLK input to the filter circuit 10, the source frequency clock is used as it is. The clock divider 22 sets the filter constant of the filter clock FCLK output to the filter circuit 10 from 2 ⁿ (2 ⁿ ) of the input source frequency clock (SCLK), the setting content (division ratio n). This is a configuration that can be determined according to The clock divider 22 may be a conventionally known one, and is not particularly described. For example, the clock divider 22 includes a divider (a counter or the like) and a selector. The above setting contents (division ratio n)
The setting is input from the outside or the like and is stored in the frequency division ratio setting register 21, and the clock frequency divider 22 generates / outputs a filter clock FCLK corresponding to the set contents.

FIG. 3B shows the filter clock FCL.
A configuration that allows K to be set to an arbitrary frequency is shown. On the right side of the figure, the filter circuit 10 of FIG. 1 is shown. As the sample clock SCLK input to the filter circuit 10, the source frequency clock is used as it is.

The frequency setting register 23 stores arbitrary frequency data set and input from outside. DDA
(Digital Differential Analyzer) The frequency converter is
It operates with the source frequency clock and generates / outputs a filter clock FCLK having the frequency stored in the frequency setting register 23.

Here, in general, the filter constant of the digital filter is on the order of several hundred μsec to several msec.
On the other hand, ICs and LSIs that constitute digital circuits are several hundreds.
It can operate on the order of MHz and several n seconds. Therefore, when the sample clock SCLK is set to a very high frequency, the noise pulse removal capability of the filter circuit 10 of the present embodiment is increased in proportion thereto, and it is constant regardless of the filter clock frequency.

In particular, as shown in FIG. 3A, the filter constant of the filter clock FCLK is changed to the sample clock SC.
In the configuration in which the LK can be selected from 2 ⁿ , the effect of the present invention that enables noise removal at a constant high frequency can be obtained more greatly. Also, as shown in FIG. 3B, even in a configuration in which the frequency of the filter clock FCLK can be set arbitrarily, the frequency setting range is widened when the number of bits of the DDA circuit is increased, so that the effect is similarly increased. .

Further, in the configuration in which the analog filter is provided outside the digital filter, even if the filter constant is variable as described above, the element constant of the external analog filter can be reduced and the common filter can be used regardless of the filter constant. Can be

Next, referring to FIGS. 4 and 5, the second
The filter circuit according to the embodiment will be described. The second embodiment and a third embodiment described later apply the features of the present invention in the filter circuit of the first embodiment to a conventional counter-memory type filter circuit. It is.

FIG. 4 is a configuration diagram of a digital filter circuit 30 according to the second embodiment. In the configuration shown in the figure, the same reference numerals are given when substantially the same configuration as the configuration shown in FIG. 1 is sufficient. That is, two-stage registers (FF1, FF1) operated by the filter clock FCLK
2) and the configuration provided by the selector S provided therebetween may be substantially the same as the configuration shown in FIG. 1 (except that the selector S is switched and controlled by the count carry signal k from the counter 31). Further, the mismatch detector and the filter clock differentiating circuit may be substantially the same as those in FIG. 1, but the output of the ExOR gate G1 in the mismatch detector is set to AN.
In addition to the D gate G3, the D-flip-flop FF5 and the AND gate G6 are also input to the OR gate G3.
7 is different from that of FIG. The output signal f of the D-flip-flop FF3 is not used for switching control of the selector S, but is used as a counter load signal i to the counter 31 via the OR gate G8. FIG. 4 (and FIG. 6) shows an example in which a filter circuit is configured for one input bit.

In FIG. 4, a D-flip-flop FF
5 and the AND gate G6 generate / generate a signal g (FCLK1 cycle width) for notifying the counter 31 when the output of the FF1 is detected by the ExOR gate G1 of the mismatch detector. This is a configuration for outputting. This signal g is input to the LD terminal of the counter 31 as the counter load signal i via the OR gate G8. The signal g is also input to the J terminal of the JK flip-flop FF6, and the FF6 outputs the next FCL.
The value of the signal g is held / output from the rise of K. That is, it holds / outputs the count enable signal h. While the count enable signal h is “1”, since “1” is always applied to the UP terminal of the counter 31,
It is counted up every time FCLK rises.

As described above, the counter 31 stores the FF1 and the F
When the output of F2 does not match (when the input signal a changes), the setting value (initial value) stored in the counter value setting register 32 is loaded, and counting is started.

The output state of the FF 6 is usually determined by the counter 31
The counter carry signal k is held until “1” is output, but the output c of the FF1 is output by the ExOR gate G1.
When it is detected that the output and the output b of the FF2 match, the count enable signal h becomes “0”.

The counter load signal i also becomes "1" when a mismatch is detected by the mismatch detector in substantially the same manner as in the first embodiment described above. Thus, if noise is detected by the mismatch detector,
You can reload and start counting again from the beginning.

An example of a specific operation of the filter circuit having the configuration shown in FIG. 4 will be described below with reference to FIG. In the example shown in FIG.
2 stores a set value '7', and the description will be made assuming that the counter 31 is a hexadecimal counter.

First, it is assumed that the input signal "a" has a short width of "1" continuously due to noise in substantially the same manner as described with reference to FIG. The output c of the FF1 becomes "1" at the sampling timing (t1) by the first "1" of the input signal "a", and the output of the ExOR gate G1 becomes "1". Therefore, the FCLK is output by the FF5 and the AND gate G6. Is generated / output, and this is input to the LD terminal of the counter 31 as the counter load signal i via the OR gate G8.
The signal g is also input to the J terminal of the FF6, and the FF6 holds / outputs the count enable signal h ('1') to the counter 31 from the next rising edge (t2) of FCLK. With such an operation, when the input signal a changes to “1” as shown in FIG. 5, the set value “7” stored in the counter value setting register 32 is loaded into the counter 31 by the counter load signal i. , And the count enable signal h becomes "1" to start counting.

Here, when the FCLK has the cycle / timing as shown in FIG. 5 with respect to the input signal a as shown in FIG. 5, in the conventional circuit, the rise of FCLK detects noise. If the input change does not occur (a circle shown by a dotted line in the figure), the counting is continued without recognizing the noise, and the noise is taken in as a result.

On the other hand, in the circuit of FIG. 4, for example, the change of the input signal a between the timings t3 and t4 (the circle shown by the dotted line) is not matched by the operation of the clock (SCLK) having a frequency higher than FCLK. Since the noise can be detected by the detector, the noise can be recognized and the counting can be restarted from the beginning.

That is, the mismatch detector detects that the input signal a and the output c of the FF1 do not match while the output c of the FF1 does not match the output b of the FF2, as shown in FIG. As described above, when "1" is output from the FF3, this is input to the counter 31 as the counter load signal i via the OR gate G8. Thus, the counter 31 reloads the set value '7' stored in the counter value setting register 32. Then, it starts counting again from the beginning.

Similarly, a short input change after the timing t6 can be detected by the mismatch detector, so that the counter 31 sets the counter value setting register 3 again as shown in FIG.
The setting value '7' stored in 2 is reloaded and counting is restarted from the beginning.

After that, since the input signal a is "1" in a normal state, the counter 31 continues counting without reloading, and when the count value becomes "f (hexadecimal)". The counter carry signal k is output as "1". The selector S is switched to the “S = 1” side by the counter carry signal k.
Becomes the input d of the FF2. As a result, the output signal b from the FF2 becomes “1” at the next rising edge of FCLK.
Becomes

As described above, the filter circuit 3 of the second embodiment
According to 0, even if the noise has a width / timing that cannot be detected by FCLK, the noise can be detected by the mismatch detector that operates on the sample clock SCLK having a higher frequency than FCLK, so the counting is restarted from the beginning. , Can be filtered successfully.

In the above-described conventional method, when the frequency of FCLK is increased to increase the noise removal capability, the number of counts required for the filter constant increases, so that the number of bits of the counter and the memory must be increased. Although the circuit scale increases in accordance with the number of bits, the filter circuit 30 of the second embodiment can increase the noise removal capability regardless of the frequency of FCLK. It is possible to improve the noise removal capability without increasing.

In the filter circuit 30 of the second embodiment, when noise is detected, counting is restarted from the beginning. However, there may be a case where it is desired to ignore a minute noise and continue.

The third embodiment will be described below with reference to FIGS. 6 and 7 for such a case. FIG.
FIG. 9 is a configuration diagram of a digital filter circuit 40 according to a third embodiment.

The filter circuit 40 shown in FIG.
Are substantially the same as those of the filter circuit 30 shown in FIG. 1 except for a part thereof. Therefore, the same components are denoted by the same reference numerals, description thereof will be omitted, and only different points will be described.

The difference is that in the filter circuit 30,
The counter 31 is configured to always input "1" to the UP terminal and count up when a clock is input in the count enable state, and the output of the FF3 of the mismatch detector is used as a load signal. In the filter circuit 40 of FIG.
In that the countdown is performed when a mismatch is detected by the mismatch detector. The difference is that the count enable signal h is not cleared except for the counter carry signal k.

An example of a specific operation of the filter circuit having the configuration shown in FIG. 6 will be described below with reference to FIG. As shown in the figure, in the filter circuit 40, the output of the FF3 of the mismatch detector is inverted and input to the UP terminal of the counter 41 by the inverter G9. Reference numeral 41 denotes a count-up mode in which the count enable signal k is "1", and the count is incremented by one at every rising edge of FCLK. On the other hand, when a mismatch is detected by the mismatch detector and is output as “1” from FF3, FCLK
Counts down by one at the rise of.

[0076]

As described in detail above, according to the digital filter of the present invention, the operation of the filter circuit is controlled by detecting noise using a noise monitoring clock having a higher frequency than the filter clock. The noise removal capability can be increased without depending on the filter constant. Furthermore, even in a configuration in which an analog filter is provided externally and a filter constant can be selected, the element constant of the externally provided analog filter can be made small and common regardless of the filter constant.

Further, when the present invention is applied to a digital filter of a counter system, the noise removing capability can be improved without increasing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital filter circuit according to a first embodiment.

FIG. 2 is a timing chart illustrating an example of a specific operation of the filter circuit of FIG. 1;

FIG. 3 is a diagram illustrating an example of a configuration that allows a plurality of filter constants to be set in the filter circuit of FIG. 1;

FIG. 4 is a configuration diagram of a digital filter circuit according to a second embodiment.

FIG. 5 is a timing chart illustrating an example of a specific operation of the filter circuit of FIG. 4;

FIG. 6 is a configuration diagram of a digital filter circuit according to a third embodiment.

FIG. 7 is a timing chart illustrating an example of a specific operation of the filter circuit of FIG. 6;

FIG. 8 is a configuration diagram of a conventional filter circuit.

FIG. 9 is a timing chart illustrating an example of a specific operation of the filter circuit of FIG. 8;

[Explanation of symbols]

 Reference Signs List 10 digital filter FF1 D flip-flop FF2 D flip-flop FF3 D flip-flop FF4 D flip-flop S selector G1 Exclusive OR (ExOR) gate G2 ExOR gate G3 AND gate G4 OR gate G5 NAND gate 21 Division ratio setting register 22 Clock division 23 Frequency setting register 24 DDA frequency converter 30 Digital filter 31 Counter 32 Counter value setting register FF5 D flip-flop FF6 JK flip-flop G6 AND gate G7 OR gate (1 terminal inverted input) G8 OR gate 40 Digital filter 41 counter 42 counter Value setting register G9 Inverter

Claims (6)

[Claims] 1. A digital filter for filtering an input signal by a two-stage sampling method, comprising a cascade-connected first and second registers operated by a filter clock corresponding to a filter constant. A digital filter, comprising: a noise detection / control unit that suppresses updating of the output of the second register when a noise component included in the input signal is detected by a high frequency noise detection clock. 2. A selector for inputting either the output of the first register or the output of the second register to the second register, wherein the noise detection / control means includes a selector for the first register. When it is detected that the output of the first register does not match the input signal when the output and the output of the second register do not match, the output of the first register changes to the second signal. 2. The digital filter according to claim 1, wherein the selector is controlled so as not to input to the register. 3. The digital filter according to claim 1, wherein the filter clock is generated at an arbitrary frequency division ratio based on the noise monitoring clock. 4. The digital filter according to claim 1, wherein the filter clock is generated as a clock having an arbitrary frequency based on the noise monitoring clock. 5. A digital filter that has first and second cascaded registers operated by a filter clock corresponding to a filter constant and filters an input signal by a counter method, wherein the frequency is higher than the filter clock. And a noise detection / control unit that operates with the noise detection clock and suppresses updating of the output of the second register when noise included in the input signal is detected. 6. The method according to claim 1, wherein the counter method is an UP-RESET.
A counter method of a mode or a counter method of an UP-DOWN mode.
In the UP-RESET mode counter method, the counter is reloaded with a set value, and the UP-DOWN
6. The digital filter according to claim 5, wherein a countdown is performed in the mode counter method.