JP2697626B2 - Lock detector for phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lock detector for a phase locked loop, and more particularly to a lock detector capable of accurately detecting lock.

[0002]

2. Description of the Related Art FIG. 9 shows a configuration example of a conventional lock detector in a phase locked loop circuit. FIG. 9 does not include the entire configuration of the phase locked loop, and includes a phase comparator 110, a charge pump circuit 111, and a low-pass filter (LPF) 11.
Only 2 is shown. The phase comparator 110 outputs a signal corresponding to a phase difference or a frequency difference between the signals of the two input signal lines 101 and 102 to the charge pump circuit 111 from the two control signal lines 121 and 122, and outputs the signal to the charge pump circuit 111. Outputs a control signal for driving the LPF 112 to the signal line 123. The LPF 112 is a signal line 123
Attenuates the high frequency components of the signal of
Output from

[0003] A conventional lock detector is a NAND circuit 13.
1, D-type flip-flop 134, NOR circuit 135,
It is composed of a counting circuit 115. Input signal line 10
The frequency is K times higher than the periodic signal input from 1;
When the periodic signal input from the input signal line 101 rises, a signal that falls without a sufficient phase difference is input from the clock signal line 107 to the flip-flop 132.
Further, the output signal of the phase comparator 110 of the phase locked loop circuit is referred to, and the sampling is performed with the periodic signal input from the clock signal line 107. When the output signal of the phase comparator 110 is active and the signal can be latched by the periodic signal input from the clock signal line 107, the phase comparator 1
Since the output of 10 indicates that a signal having a certain width is output, the lock signal line 103 becomes low level, indicating that the phase locked loop is not locked.

On the other hand, when the phase locked loop is locked,
Since the output signal of the phase comparator 110 has a small active period, the signal cannot be latched by the periodic signal input from the clock signal line 107. At this time, since the counting circuit 115 is activated by the signal 124 from the NOR circuit 135, the periodic signal 125 input from the input signal line 101 is counted. When the count value reaches a predetermined count value, the count circuit 115 activates the output. Also,
When this output becomes active, the lock signal becomes active.

When the output signal of the phase comparator 110 is active, the signal can be latched by the periodic signal input from the clock signal line 107, and the counting circuit is initialized by the signal 124. Lock status is prevented from being output erroneously.

[0006]

In the conventional lock detector shown in FIG. 9, in order to determine that the phase locked loop is locked, the frequency of the periodic signal input from the input signal line 101 is changed. When the periodic signal input from the input signal line 101 rises by K times, it is necessary to input from the clock signal line 107 a signal that falls without a sufficient phase difference.

By increasing the value of K, it is possible to determine a more strict lock state.
When a periodic signal input from 01 rises, it has been difficult to create a signal that falls without a sufficient phase difference. Therefore, it was necessary to reduce the value of K to some extent.

An object of the present invention is to provide an accurate and high-speed lock detector that eliminates such conventional disadvantages.

[0009]

According to the present invention, there is provided a lock detector for a phase locked loop circuit, which outputs a signal corresponding to a phase difference or a frequency difference between first and second input signals from one or more signal lines. A phase comparator that outputs from a first control signal comprising:
A charge pump circuit that receives the control signal of (a) as an input and obtains a second control signal for driving a low-pass filter;
, And a low-pass filter for attenuating the high-frequency component of the second control signal, and N voltage-controlled delay elements 1, 2,. . . , N are connected in a ring shape, and the output terminal of the low-pass filter is connected to the N voltage-controlled delay elements 1, 2,. . . , N to control the oscillation frequency from the outside and to obtain an output signal from the output terminal of the voltage-controlled delay element N, and to the output of the voltage-controlled delay element N of the voltage-controlled oscillator , The control terminal is the output terminal of the low-pass filter.
And K voltage-controlled delay elements connected to the phase-comparator, wherein a first input signal of the phase comparator is provided as an output signal of the voltage-controlled oscillator, and a second input signal of the phase comparator is In a phase locked loop provided by an external reference clock, two signals obtained from an output terminal of a voltage controlled delay element (NK) and an output terminal of a voltage controlled delay element (N + K) constituting the voltage controlled oscillator are used. A lock detection circuit that detects that the phase of the external reference clock is included between the phases, and a countable state and an initial state are selected by a signal obtained from an output terminal of the lock detection circuit, A counting circuit for counting the external reference clock, and detecting a locked state of the phase locked loop.

Further, the lock detector of the phase locked loop of the present invention provides a signal corresponding to a phase difference or a frequency difference between the first and second input signals, the signal comprising a first or more signal line.
And a charge pump circuit that receives the first control signal as input and obtains a second control signal for driving the low-pass filter, and a second control signal that receives as input a second control signal. A low-pass filter for attenuating the high frequency components of the control signal, and N voltage-controlled delay elements 1 and 1 that can control the delay time between input and output from an external control terminal.
2,. . . , N are connected linearly, and the output terminal of the low-pass filter is connected to the N voltage-controlled delay elements 1, 2,. . . Can control the delay time between the input and output from the externally connected to the control terminal of N, said voltage system
A voltage control delay circuit for inputting a second input signal to an input of the control delay element 1 and obtaining an output signal from an output terminal of the voltage control delay element N;
The control terminal is connected to the output of the low-pass filter.
K voltage control delay elements connected to the output terminal ,
In a phase synchronization circuit, a first input signal of the phase comparator is provided as an output signal of the voltage control delay circuit, and a second input signal of the phase comparator is provided with an external reference clock. The phase of the external reference clock between the phase of the two signals obtained from the output terminal of the voltage control delay element (N−K) and the output terminal of the voltage control delay element (N + K) constituting the voltage control delay circuit A lock detection circuit that detects that a lock state is contained, a countable state and an initial state are selected by a signal obtained from an output terminal of the lock detection circuit, and a counting circuit that counts the external reference clock. And detecting a locked state of the phase synchronization circuit.

[0011]

When the phase locked loop is locked, the phase of the output signal fluctuates in time. This fluctuation hinders accurate and high-speed lock detection.

On the other hand, according to the present invention, the output signal of the phase locked loop is obtained by the voltage controlled oscillator or the voltage controlled delay circuit which is formed by connecting the voltage controlled delay elements in a ring or linear shape. From the voltage-controlled delay element connected before and after the voltage-controlled delay element that obtains the output signal, it is possible to easily obtain a signal that is slightly delayed in phase from the phase of the output signal and a signal that is slightly advanced in phase. The phase of the signal delayed in phase and the phase of the signal advanced in phase also fluctuates in time, but an external reference between the signal delayed in phase and the signal advanced in phase. By detecting that the clock is in the locked state if it has a phase, it eliminates the effects of temporal fluctuation of the phase,
The locked state of the phase locked loop can be detected accurately and at high speed.

[0013]

FIG. 1 is a circuit diagram showing a lock detector of a phase locked loop circuit according to a first embodiment of the present invention.

The phase locked loop circuit according to this embodiment outputs a signal corresponding to a phase difference or a frequency difference between two input signals of an input signal line 101 and an output signal line 102 through control signal lines 121 and 122. Vessel 110,
A charge pump circuit 111 that receives the signals of the control signal lines 121 and 122 as inputs and obtains a control signal for driving the low-pass filter 112 on the control signal line 123, and a control signal of the control signal line 123 that is an input. A low-pass filter 112 for attenuating frequency components, and N voltage-controlled delay elements 116 (1)... Capable of controlling a delay time between input and output from an external control terminal. . . 116 (N) are connected in a ring shape, and the voltage control delay element 11
A voltage-controlled oscillator 113 that obtains an output signal from the output terminal 6 (N), and a voltage-controlled oscillator 113 that is linearly connected to the output of the N-th stage voltage-controlled delay element 116 (N) of the voltage-controlled oscillator 113.
And voltage control delay elements 116 (N + 1).

The oscillation frequency of the voltage controlled oscillator 113 is determined by connecting the output terminal of the low-pass filter 112 to the N voltage controlled delay elements 116 (1). . . 11
6 (N) can be controlled from the outside by connecting to the control terminal. A first input signal of the phase comparator 110 is provided from the output signal line 102 as an output signal of the voltage controlled oscillator 113, and a second input signal of the phase comparator 110 is provided from the input signal line 101. It is.

The lock detector of this embodiment is a voltage-controlled delay element 116 (N-1) constituting the voltage-controlled oscillator 113.
And a signal obtained from the output terminal of the voltage-controlled delay element 116 (N + 1) connected to the voltage-controlled oscillator 113 via the output signal line 105. A lock detection circuit 114 for detecting that the phase of a reference clock from the outside enters between the signal phases, and a countable state and an initial state are selected by a signal obtained from an output terminal 124 of the lock detection circuit 114. And a counting circuit 115 for counting an external reference clock, and detects a locked state of the phase synchronization circuit.

FIG. 2 shows an example of the configuration of the phase comparator 110. This phase comparator has a two-input NAND circuit, a three-input N
It is composed of an AND circuit and a 4-input NAND circuit. In the figure, reference numerals 121 and 122 indicate output signal lines.

FIG. 3 shows a configuration example of the charge pump circuit 111. This charge pump circuit includes an inverter circuit and a pMOS transistor and an nMOS transistor. In the figure, reference numeral 123 denotes an output signal line.

FIG. 4 shows an example of the configuration of the low-pass filter 112. This low-pass filter is composed of a resistor and a capacitor. In the figure, reference numeral 106 denotes a control signal line.

As shown in FIG. 1, the lock detection circuit 114 includes D-type flip-flops 10 and 12 and an inverter 1
2 and an AND circuit 16. The reference clock of the input signal line 101 is input to clock input terminals of the D-type flip-flops 10 and 12. The output signal lines 104 and 105 are connected to the D input terminals of the D flip-flops 10 and 14, respectively.

FIG. 5 shows an example of the configuration of the counting circuit 115.
The counting circuit 115 includes AND circuits 18, 20, 22,
24 and D-type flip-flops 26, 28, 30, 32,
34.

Next, the operation of this embodiment will be described.

The lock detector of the phase locked loop circuit of this embodiment has two output signal lines 1 obtained from the voltage controlled delay element 116 constituting the voltage controlled oscillator 113 of the phase locked loop circuit.
This is performed by comparing the signals 04 and 105 with the reference clock of the input signal line 101. Here, the signal line 10
4, a signal whose phase is advanced from the signal of the output signal line 102 of the voltage controlled oscillator 113 is obtained, and a signal whose phase is delayed from the output signal 102 of the voltage controlled oscillator 113 is obtained from the signal line 105. The locked state of the phase locked loop is determined by comparing the signals obtained from the signal lines 104 and 105 in synchronization with the reference clock obtained from the input signal line 101. In the configuration example shown in FIG. 1, when the lock state is detected a plurality of times using the counting circuit 115, it is determined that the lock state is established.

When the phase locked loop is locked, the phase of the output signal fluctuates in time. The signals obtained from the signal lines 104 and 105 also have temporal fluctuations, but if the phase of the external reference clock is included between the delayed signal and the advanced signal. By detecting the locked state, the influence of the temporal fluctuation of the phase can be removed, and the locked state of the phase locked loop can be accurately and quickly detected.

FIG. 6 shows a second configuration example of the voltage controlled oscillator. In contrast to the voltage-controlled oscillator 113 shown in FIG.
Signal line 104 for obtaining a signal advanced in phase from the signal No. 02
And the position of the voltage-controlled delay element to which the signal line 105 for obtaining a signal delayed in phase from the output signal 102 of the voltage-controlled oscillator is different. That is, N of the voltage controlled oscillator 113
Two voltage control delay elements 116 (N + 1) and 116 (N + 2) are linearly connected to the output of the voltage control delay element 116 (N) at the stage, and the signal line 104 is connected to the voltage control delay element (N− The signal line 105 is connected to the output terminal of the voltage control delay element (N + 2).

Generally, when the number of voltage-controlled delay elements constituting a voltage-controlled oscillator is N and an output signal is obtained from the output of the N-th voltage-controlled delay element, the output of the N-th voltage-controlled delay element is Further, the K voltage-controlled delay elements are connected in a straight line, and the signal line 104 that obtains a signal whose phase is advanced from the output signal is delayed from the output signal by the (NK) -th stage voltage-controlled delay element. The signal line 105 for obtaining a signal is (N +
K) It can be obtained from each of the voltage control delay elements in the stage.

When the number of voltage-controlled delay elements constituting the voltage-controlled oscillator is N and an output signal is obtained from the output of the N-th stage voltage-controlled delay element, a signal line for obtaining a signal whose phase is ahead of the output signal The signal line 104 can be obtained from the (NK) th stage voltage controlled delay element, and the signal line 105 for obtaining a signal delayed in phase from the output signal can be obtained from the Kth stage voltage controlled delay element. Here, lock detection can be performed more strictly as K is smaller.

Further, by inserting a frequency divider between the output signal line 102 of the voltage controlled oscillator 113 and the phase comparator 110, the phase locked loop circuit of the present invention can obtain a frequency multiplied by the input frequency. The detector is applicable.

FIG. 7 is a circuit diagram showing a lock detector of the phase locked loop circuit according to the second embodiment of the present invention.

The phase locked loop circuit according to this embodiment converts a signal corresponding to the phase difference or frequency difference between two input signals into
A phase comparator 110 that outputs through control signal lines 121 and 122, and a control signal line 123 that receives the control signal lines 121 and 122 and drives a low-pass filter 112.
And a control signal line 123
, And a low-pass filter 112 for attenuating high frequency components of the control signal line 123, and N voltage-controlled delay elements 116 (1). . . The input / output terminals 116 (N) are connected linearly, and the output terminal of the low-pass filter 112 is connected to the N voltage control delay elements 1 by the control signal line 106.
16 (1). . . A voltage-controlled delay circuit 117 connected to a control terminal of the voltage-controlled delay element 116 (N) to obtain an output signal from an output terminal of the voltage-controlled delay element 116 (N); One voltage-controlled delay element 116 (N + 1) is linearly connected to the output of the 117th voltage-controlled delay element 116 (N).

A first input signal of the phase comparator 110 is provided from the output signal line 102 as an output signal of the voltage control delay circuit 117, and a second input signal of the phase comparator 110 is provided from the input signal line 101. This is the reference clock from.

The lock detector of the present embodiment includes a voltage control delay element 116 (N-
The signal obtained from the output terminal of 1) via the output signal line 104 and the output signal line 1 from the output terminal of the voltage control delay element 116 (N + 1) connected to the voltage control delay circuit 117.
A lock detector circuit 114 for detecting that the phase of an external reference clock is between the phases of the two signals with the signal obtained through the signal line 05, and a lock detection circuit 114
And a counting circuit 115 for selecting a countable state and an initial state based on a signal obtained from the output terminal 124 of the external device, and counting an external reference clock.

The lock detector of the phase locked loop circuit of this embodiment is performed by comparing each signal of the two signal lines 104 and 105 with the reference clock of the input signal line 101.
Here, a signal whose phase is advanced from the signal of the output signal line 102 of the voltage control delay circuit 117 is obtained from the signal line 104, and the signal of which the phase is higher than the signal of the output signal line 102 of the voltage control delay circuit 117 is obtained from the signal line 105. A delayed signal is obtained.
The signal obtained from the signal lines 104 and 105 is input signal line 1
The locked state of the phase-locked loop is determined by comparing the signals obtained from the phase-locked loop 01 with each other in synchronization. In the configuration example shown in FIG. 7, when the locked state is detected a plurality of times using the counting circuit 115, it is determined that the locked state is established.

When the phase locked loop is in the locked state, the phase of the output signal has a temporal fluctuation. Signal line 104
The signal obtained from the signal line 105 also has a temporal fluctuation, but if the phase of the external reference clock is inserted between the delayed signal and the advanced signal, the signal is locked. By detecting that there is, it is possible to remove the influence of the temporal fluctuation of the phase and accurately and quickly detect the locked state of the phase locked loop.

FIG. 8 shows a second configuration example of the voltage control delay circuit. In contrast to the first voltage control delay circuit shown in FIG. 7, the second voltage control delay circuit 117 includes a signal line 104 for obtaining a signal whose phase is advanced from the output signal 102 of the voltage control delay circuit.
And the position of the voltage control delay element to which the signal line 105 for obtaining a signal delayed in phase from the output signal 102 of the voltage control delay circuit is different. That is, the two voltage-controlled delay elements 116 (N + 1) and 116 (N + 2) are linearly connected to the output of the voltage-controlled delay element 116 (N) of the Nth stage of the voltage-controlled delay circuit, and Is connected to the output terminal of the voltage control delay element (N-2), and the signal line 105 is connected to the output terminal of the voltage control delay element (N + 2).

Generally, when the number of voltage control delay elements constituting a voltage control delay circuit is N and an output signal is obtained from the output of the N-th voltage control delay element, the output of the N-th voltage control delay element The signal line 104, which further connects K voltage-controlled delay elements in a straight line and obtains a signal whose phase is advanced from the output signal, is delayed from the (NK) -th stage voltage-controlled delay element by a phase lag from the output signal. The signal line 105 for obtaining the
+ K) can be obtained from the respective voltage control delay elements. Lock detection can be performed more strictly as K is smaller.

[0037]

As described above, when the phase locked loop is in the locked state, the phase of the output signal has a temporal fluctuation. This fluctuation hinders accurate and high-speed lock detection.

The lock detector of the conventional phase locked loop circuit shown in FIG. 9 cannot perform accurate and high speed lock detection because a separate high-speed clock signal is required. When the output signal of the circuit is obtained by a voltage-controlled oscillator or a voltage-controlled delay circuit configured by connecting the voltage-controlled delay elements in a ring or straight line,
Focusing on the fact that a signal slightly delayed in phase and a signal advanced slightly in phase from the phase of the output signal can be easily obtained from the voltage control delay element connected before and after the voltage control delay element obtaining the output signal. , By detecting that the phase of the reference clock from the outside is between the delayed signal and the advanced signal, it is in the locked state,
It is possible to detect the locked state of the phase-locked loop accurately and at high speed by removing the influence of the temporal fluctuation of the phase.

[Brief description of the drawings]

FIG. 1 is a diagram showing a block configuration of a lock detector of a phase locked loop according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a specific example of the phase comparator of FIG. 1;

FIG. 3 is a diagram showing a specific example of the charge pump circuit of FIG. 1;

FIG. 4 is a diagram showing a specific example of the low-pass filter of FIG.

FIG. 5 is a diagram showing a specific example of the counting circuit of FIG. 1;

FIG. 6 is a diagram showing a block configuration of a voltage controlled oscillator according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a block configuration of a lock detector of the phase locked loop circuit of FIG. 6;

FIG. 8 is a diagram showing a block configuration of a voltage control delay circuit of FIG. 6;

FIG. 9 is a diagram showing a block configuration of a lock detector of a conventional phase locked loop circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Input signal line 102, 104, 105 Output signal line 103 Lock signal line 106 Control signal line 107 Clock signal line 110 Phase comparator 111 Charge pump 112 Low-pass filter 113 Voltage control oscillator 114 Lock detection circuit 115 Counting circuit 116 Voltage control delay element 117 Voltage control delay circuit

Claims (4)

(57) [Claims] 1. A phase comparator for outputting a signal corresponding to a phase difference or a frequency difference between first and second input signals from a first control signal comprising one or more signal lines; A charge pump circuit that receives the control signal of (i) and obtains a second control signal for driving the low-pass filter;
A low-pass filter that receives a second control signal as input and attenuates a high-frequency component of the second control signal; and N that can control a delay time between input and output from an external control terminal.
Voltage control delay elements 1, 2,. . . , N are connected in a ring shape, and the output terminal of the low-pass filter is connected to the N voltage-controlled delay elements 1,
2,. . . , N connected to control terminals of the voltage-controlled delay element N, which can control the oscillation frequency from the outside and obtain an output signal from the output terminal of the voltage-controlled delay element N ; Connect the control terminal to the output terminal of the low-pass filter.
And a K-number of the voltage-controlled delay element which continues the first input signal of the phase comparator is provided by the output signal of said voltage controlled oscillator, a second input signal of the phase comparator from the outside In the phase-locked loop provided by the reference clock, the voltage-controlled delay element (N-
A lock detection circuit for detecting that the phase of the external reference clock is between the phases of the two signals obtained from the output terminal of K) and the output terminal of the voltage control delay element (N + K); A counting circuit that selects a countable state and an initial state by a signal obtained from an output terminal of the lock detection circuit, and counts the external reference clock, and detects a lock state of the phase synchronization circuit. A lock detector for a phase locked loop. 2. A phase comparator for outputting a signal corresponding to a phase difference or a frequency difference between first and second input signals from a first control signal comprising one or more signal lines; A charge pump circuit that receives a second control signal as input and obtains a second control signal for driving a low-pass filter, and a low-pass filter that receives second control signal as input and attenuates a high frequency component of the second control signal And the delay time between input and output can be controlled from an external control terminal.
Voltage control delay elements 1, 2,. . . , N are connected in a ring shape, and the output terminal of the low-pass filter is connected to the N voltage-controlled delay elements 1,
2,. . . , N to control the oscillation frequency from the outside, and obtain an output signal from the output terminal of the voltage-controlled delay element N; and a first input signal of the phase comparator is the voltage-controlled oscillator. And the second input signal of the phase comparator is provided by an external reference clock, wherein the voltage controlled delay element (N−
A lock detection circuit for detecting that the phase of the external reference clock is between the phases of the two signals obtained from the output terminal of K) and the output terminal of the voltage control delay element ( N ); A counting circuit that selects a countable state and an initial state by a signal obtained from an output terminal of the lock detection circuit, and counts the external reference clock, and detects a lock state of the phase synchronization circuit. A lock detector for a phase locked loop. 3. A frequency divider for dividing the output signal of the voltage controlled oscillator between an output terminal of the voltage controlled oscillator and a terminal of the phase comparator to which a first input signal is input. The lock detector for a phase-locked loop according to claim 1, further comprising: 4. A phase comparator for outputting a signal corresponding to a phase difference or a frequency difference between first and second input signals from a first control signal comprising one or more signal lines; A charge pump circuit that receives a second control signal as input and obtains a second control signal for driving a low-pass filter, and a low-pass filter that receives second control signal as input and attenuates a high frequency component of the second control signal And the delay time between input and output can be controlled from an external control terminal.
Voltage control delay elements 1, 2,. . . , N are connected in a straight line, and the output terminal of the low-pass filter is connected to the N voltage-controlled delay elements 1,
2,. . . It can control the delay time between the input and output from the externally connected to the control terminal of N, the input of the voltage controlled delay element 1
Enter a second input signal, a voltage control delay circuit for obtaining an output signal from the output terminal of the voltage controlled delay element N, is connected to the output of the voltage controlled delay element N of the voltage controlled delay circuit, the low-pass control terminal To the output terminal of the filter
K voltage-controlled delay elements connected thereto, wherein a first input signal of the phase comparator is provided as an output signal of the voltage-controlled delay circuit, and a second input signal of the phase comparator is externally provided. Of the two signals obtained from the output terminal of the voltage-controlled delay element (NK) and the output terminal of the voltage-controlled delay element (N + K) constituting the voltage-controlled delay circuit. A lock detection circuit that detects that the phase of the external reference clock is included between phases, and a countable state and an initial state are selected by a signal obtained from an output terminal of the lock detection circuit, A lock circuit for counting a reference clock from the outside, wherein a lock state of the phase locked loop circuit is detected.