JPS6461119A - Pll unlock state detection circuit - Google Patents

Abstract

PURPOSE:To eliminate the delay by anunlock state deteciton inhibiting period in the presence of a time constant circuit by using a delay circuit, a sequential circuit such as a D flip-flop and a logic circuit such as a NAND circuit so as to detect the unlock state of a clock extraction PLL circuit. CONSTITUTION:When the phase shift width (p) is larger than a difference (r) between the phase difference pi/2rad and the delay width (q) of the 2nd delay circuit 72, a low level of an output signal f2 of a PLL circuit (comprising of circuits 2-5) is latched by a leading edge of a signal f1d being the result of retarding an input signal f2 to the PLL circuit (comprising of circuits 2-5) by the 1st delay circuit 71. Moreover, a low level of a delay signal f2d of the output signal f2 is latched at the trailing edge of the input signal f1. Thus, an output signal (n) of a NAND circuit 75 receiving output signals l, m of two D flip-flops 73, 74 reaches a high level thereby detecting the unlock state. Thus, the unlock state of the PLL circuits is detected immediately without any delay.