JPS6424630A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPS6424630A JPS6424630A JP62181980A JP18198087A JPS6424630A JP S6424630 A JPS6424630 A JP S6424630A JP 62181980 A JP62181980 A JP 62181980A JP 18198087 A JP18198087 A JP 18198087A JP S6424630 A JPS6424630 A JP S6424630A
- Authority
- JP
- Japan
- Prior art keywords
- flip
- circuit
- flop circuit
- terminal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Optical Recording Or Reproduction (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To set the phase deviation at the time of detecting lock with high accuracy by adopting the constitution such that the output pulse of a phase comparing circuit is applicable to a clock input terminal of a flip-flop circuit and applicable also to a terminal D via a delay circuit in an optical disk test system. CONSTITUTION:Output pulses PU, PD obtained from a phase comparating circuit 1 are fed to the clock input terminal of a flip-flop circuit 8 via a logic circuit 6 and also fed to a terminal D of the flip-flop circuit 8 via a delay circuit 7. The state of signal at the terminal D is fetched at the leading edge of the pulse signal fed to the clock input terminal in the flip-flop circuit 8. An output signal SL obtained from the flip-flop circuit 8 is used as a lock detection signal. In such a case, a changeover switch 9 is switched in response to the input frequency and the output of a prescribed flip-flop circuit is selected, then the locking state is always detected at a constant phase deviation even when the input frequency is changed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62181980A JPS6424630A (en) | 1987-07-21 | 1987-07-21 | Pll circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62181980A JPS6424630A (en) | 1987-07-21 | 1987-07-21 | Pll circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6424630A true JPS6424630A (en) | 1989-01-26 |
Family
ID=16110219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62181980A Pending JPS6424630A (en) | 1987-07-21 | 1987-07-21 | Pll circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6424630A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5555278A (en) * | 1992-09-21 | 1996-09-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor circuit having phase lock function |
| WO1996029785A1 (en) * | 1995-03-17 | 1996-09-26 | Hitachi, Ltd. | Variable loop gain frequency synthesizer |
| US5978427A (en) * | 1996-08-28 | 1999-11-02 | Nec Corporation | Phase-locked loop circuit having a lock state detecting function |
| JP2011139436A (en) * | 2009-12-31 | 2011-07-14 | Lg Display Co Ltd | Method and apparatus for detecting jitter of phase locked loop |
| US8071053B2 (en) | 2006-04-06 | 2011-12-06 | A & T Corporation | Dispensing apparatus |
-
1987
- 1987-07-21 JP JP62181980A patent/JPS6424630A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5555278A (en) * | 1992-09-21 | 1996-09-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor circuit having phase lock function |
| WO1996029785A1 (en) * | 1995-03-17 | 1996-09-26 | Hitachi, Ltd. | Variable loop gain frequency synthesizer |
| US5978427A (en) * | 1996-08-28 | 1999-11-02 | Nec Corporation | Phase-locked loop circuit having a lock state detecting function |
| US8071053B2 (en) | 2006-04-06 | 2011-12-06 | A & T Corporation | Dispensing apparatus |
| JP2011139436A (en) * | 2009-12-31 | 2011-07-14 | Lg Display Co Ltd | Method and apparatus for detecting jitter of phase locked loop |
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