JPS6453624A - Clock interruption detecting circuit - Google Patents

Clock interruption detecting circuit

Info

Publication number
JPS6453624A
JPS6453624A JP62210980A JP21098087A JPS6453624A JP S6453624 A JPS6453624 A JP S6453624A JP 62210980 A JP62210980 A JP 62210980A JP 21098087 A JP21098087 A JP 21098087A JP S6453624 A JPS6453624 A JP S6453624A
Authority
JP
Japan
Prior art keywords
circuit
clock
output signal
exclusive
delaying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62210980A
Other languages
Japanese (ja)
Inventor
Minoru Seki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62210980A priority Critical patent/JPS6453624A/en
Publication of JPS6453624A publication Critical patent/JPS6453624A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate externally fitted parts and to miniaturize the circuit by detecting the interruption of a clock only by a delaying element, an exclusive OR circuit and the logical circuit of FF. CONSTITUTION:When a clock 6 is inputted to be observed to a data input terminal 4 at a time (t0), an output signal 7 delayed only by one period is outputted from a delaying circuit 2. Then, the output signal 7 of the clock 6 and the delaying circuit 2 is inputted to an exclusive OR circuit 3, both signals are of the same phase and clock width, and therefore, an output signal 8 of the exclusive OR circuit 3 is a low level and an output signal 9 of a TFF1 is a low level. When the clock 6 to be observed at a time (t1) is stopped, the output signal 8 of the exclusive OR circuit 3 becomes a high level and the output signal 9 of the TFF1 is changed to the high level. Consequently, the clock interruption can be detected.
JP62210980A 1987-08-24 1987-08-24 Clock interruption detecting circuit Pending JPS6453624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62210980A JPS6453624A (en) 1987-08-24 1987-08-24 Clock interruption detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62210980A JPS6453624A (en) 1987-08-24 1987-08-24 Clock interruption detecting circuit

Publications (1)

Publication Number Publication Date
JPS6453624A true JPS6453624A (en) 1989-03-01

Family

ID=16598313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62210980A Pending JPS6453624A (en) 1987-08-24 1987-08-24 Clock interruption detecting circuit

Country Status (1)

Country Link
JP (1) JPS6453624A (en)

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