JPS6472362A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To surely execute a read-out/reproducing operation of a data by making an output waveform of a buffer amplifier corresponding to a phase lead (INC) signal, different from an output waveform of a buffer amplifier corresponding to a phase lag (DEC) signal. CONSTITUTION:When an input potential goes to high by an INC signal, and a transistor 41 is turned off, a current flows to a capacitor 42, and the capacitor 42 is charged, therefore, the rise of an output voltage waveform goes to dull. On the other hand, when the transistor 41 is turned on by a DEC signal, the capacitor 42 is discharged and a fall of the output voltage waveform goes to steep to some extent thereby, but an output characteristic being roughly equal to the above case when the capacitor 42 does not exist is offered. That is, an output waveform of a buffer amplifier 4a becomes different from a voltage waveform corresponding to the INC signal and a voltage waveform corresponding to the DEC signal. Accordingly, with respect to a regular peak shift phenomenon, a timing signal is not stabilized except its original synchronous point. In such a way, a read-out/reproducing operation of a data can be executed surely.