JPS57173783A - Watch circuit with unvolatile memory - Google Patents
Watch circuit with unvolatile memoryInfo
- Publication number
- JPS57173783A JPS57173783A JP6002181A JP6002181A JPS57173783A JP S57173783 A JPS57173783 A JP S57173783A JP 6002181 A JP6002181 A JP 6002181A JP 6002181 A JP6002181 A JP 6002181A JP S57173783 A JPS57173783 A JP S57173783A
- Authority
- JP
- Japan
- Prior art keywords
- frequency division
- division circuit
- unvolatile memory
- rear stage
- unvolatile
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G3/00—Producing timing pulses
- G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
- G04G3/025—Circuits for deriving low frequency timing pulses from pulses of higher frequency by storing time-date which are periodically investigated and modified accordingly, e.g. by using cyclic shift-registers
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Electric Clocks (AREA)
Abstract
PURPOSE:To unnecessitate the input resistor of an unvolatile memory by giving data for writing in the unvolatile memory from frequency division for clock. CONSTITUTION:The input line of an unvolatile memory 5 is connected to the rear stage frequency division circuit 2b of a frequency division circuit 2 for watch. The reset terminal R or the set terminal S of the rear stage frequency division circuit 2b is used to make the rear stage frequency division circuit 2b all ''0'' or ''1'', and a voltage is applied to a wire VH for writing to write in the unvolatile memory 5 the content of rear stage frequency division circuit 26b. Based on the data written in the unvolatile memory 5, an adjustment device 7 adjusts the frequency of oscillation of a time standard oscillation source 1. If an input terminal T for testing is provided, this input terminal T is also used as an external terminal for writing data, and external clock signal may be forcibly applied to it.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6002181A JPS57173783A (en) | 1981-04-21 | 1981-04-21 | Watch circuit with unvolatile memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6002181A JPS57173783A (en) | 1981-04-21 | 1981-04-21 | Watch circuit with unvolatile memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57173783A true JPS57173783A (en) | 1982-10-26 |
Family
ID=13129985
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6002181A Pending JPS57173783A (en) | 1981-04-21 | 1981-04-21 | Watch circuit with unvolatile memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57173783A (en) |
-
1981
- 1981-04-21 JP JP6002181A patent/JPS57173783A/en active Pending
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