JPS5768929A - Flip-flop circuit - Google Patents

Flip-flop circuit

Info

Publication number
JPS5768929A
JPS5768929A JP55145459A JP14545980A JPS5768929A JP S5768929 A JPS5768929 A JP S5768929A JP 55145459 A JP55145459 A JP 55145459A JP 14545980 A JP14545980 A JP 14545980A JP S5768929 A JPS5768929 A JP S5768929A
Authority
JP
Japan
Prior art keywords
terminal
low
hazard
changes
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55145459A
Other languages
Japanese (ja)
Inventor
Hitoshi Funadogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55145459A priority Critical patent/JPS5768929A/en
Publication of JPS5768929A publication Critical patent/JPS5768929A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Abstract

PURPOSE:To avoid hazard at an output termial, by providing another input terminal to a gate casuing hazard for the output and supplying a preset signal, when a clock pulse is applied to a D type edge trigger FF circuit. CONSTITUTION:Another terminal is provided at an NAND gate 3 of an FF circuit and this is connected to a preset terminal 7. When a terminal 7 and a clear terminal 8 are respectively ''high'' and clock terminal 9 and data terminal 10 are respectively ''low'', a terminal 11 is ''low'', terminals 12-14 are ''high'', output terminal 15 is ''low'' and output terminal 16 is ''high''. When the terminal 7 changes from ''high'' to ''low'', the terminal 11 changes from ''low'' to ''high'', and the terminal changes from ''low'' to ''high'' and the terminal 16 changes from ''high'' to ''low''. When a clock pulse is applied to the terminal 9, since a signal of ''low'' is supplied from the terminal 7 to the gate 3 terminal of the terminal 13, no change is made from the delay time of gate one stage's share in the state of ''high'' to ''low'', no hazard is caused to the terminal 13 to be a constant level, and no hazard is caused to the terminal 16.
JP55145459A 1980-10-17 1980-10-17 Flip-flop circuit Pending JPS5768929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55145459A JPS5768929A (en) 1980-10-17 1980-10-17 Flip-flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55145459A JPS5768929A (en) 1980-10-17 1980-10-17 Flip-flop circuit

Publications (1)

Publication Number Publication Date
JPS5768929A true JPS5768929A (en) 1982-04-27

Family

ID=15385713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55145459A Pending JPS5768929A (en) 1980-10-17 1980-10-17 Flip-flop circuit

Country Status (1)

Country Link
JP (1) JPS5768929A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200649A (en) * 1990-11-28 1993-04-06 Sumitomo Electric Industries, Ltd. Flip-flop circuit with decreased time required from take in of data input to setting of data output
US5323065A (en) * 1991-08-08 1994-06-21 Fujitsu Limited Semiconductor integrated circuit device having edge trigger flip-flop circuit for decreasing delay time

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5186953A (en) * 1975-01-28 1976-07-30 Hitachi Ltd Furitsupu furotsupukairo
JPS5518830B2 (en) * 1977-05-04 1980-05-21

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5186953A (en) * 1975-01-28 1976-07-30 Hitachi Ltd Furitsupu furotsupukairo
JPS5518830B2 (en) * 1977-05-04 1980-05-21

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200649A (en) * 1990-11-28 1993-04-06 Sumitomo Electric Industries, Ltd. Flip-flop circuit with decreased time required from take in of data input to setting of data output
US5323065A (en) * 1991-08-08 1994-06-21 Fujitsu Limited Semiconductor integrated circuit device having edge trigger flip-flop circuit for decreasing delay time

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