JPS6419822A - Delay circuit - Google Patents

Abstract

PURPOSE:To constitute a delay circuit whose control circuit is simple by using a first in/first out memory, delaying the input of a reading pulse by an arbitrary value from the input of a writing pulse and arbitrarily setting a delay time. CONSTITUTION:The first in/first out memory(FIFO memory) 1, a counter 2, a flip flop 3, an AND gate circuit 4 are provided. A delay quantity setting value 9 is written in the counter by the pulse 8 to set an initial value. When the pulse 7 is inputted to the writing pulse input terminal W of the FIFO memory 1, input data 5 is written sequentially in the FIFO memory 1. In the counter 2, the pulse 7 is counted. When the counted value of the counter 2 coincides with the initial value, the pulse 7 is inputted to a reading pulse input terminal R and output data 10 is transmitted in the sequence of inputting. Accordingly, the initial value set to the counter 2 is changed, the quantity of arbitrary delay is obtained between the input data 5 and the output data 10.