JPS5693423A - Signal discriminating device - Google Patents
Signal discriminating deviceInfo
- Publication number
- JPS5693423A JPS5693423A JP16945479A JP16945479A JPS5693423A JP S5693423 A JPS5693423 A JP S5693423A JP 16945479 A JP16945479 A JP 16945479A JP 16945479 A JP16945479 A JP 16945479A JP S5693423 A JPS5693423 A JP S5693423A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- input
- terminal
- sampled
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
- G01R29/0273—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
Abstract
PURPOSE:To control the width of a pulse to be discriminated by the clock signal, by connecting the storage output of the fundamental memory circuit to the input of the next stage and by comparing the logical value of each stage with the input signal and by transferring it to the next stage only when they coincide with each other. CONSTITUTION:Respective output terminals 12, 13, 14 and 15 of fundamental memory circuits 3, 4, 5 and 6 are initialized by the preset signal applied to terminal 7 and the preset polarity signal applied to terminal 8. By the signal input from sample clock terminal 2, the signal input from terminal 1 is sampled in circuit 3 as it is, and this signal is compared with the storage output signal of the fundamental memory circuit of the preceding stage respectively and is sampled only for coincidence in circuits 4, 5 and 6. By this method, the clock signal having period T shorter than time width T of logic change of the input signal is input to this device together with the input signal to obtain the output where logic change components of the input signal of (n+ or -1)XT time width or less are eliminated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16945479A JPS5693423A (en) | 1979-12-27 | 1979-12-27 | Signal discriminating device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16945479A JPS5693423A (en) | 1979-12-27 | 1979-12-27 | Signal discriminating device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5693423A true JPS5693423A (en) | 1981-07-29 |
Family
ID=15886887
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16945479A Pending JPS5693423A (en) | 1979-12-27 | 1979-12-27 | Signal discriminating device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5693423A (en) |
-
1979
- 1979-12-27 JP JP16945479A patent/JPS5693423A/en active Pending
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