JPS56152060A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS56152060A JPS56152060A JP5605580A JP5605580A JPS56152060A JP S56152060 A JPS56152060 A JP S56152060A JP 5605580 A JP5605580 A JP 5605580A JP 5605580 A JP5605580 A JP 5605580A JP S56152060 A JPS56152060 A JP S56152060A
- Authority
- JP
- Japan
- Prior art keywords
- mode
- external memory
- data
- opened
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/0623—Address space extension for memory modules
Abstract
PURPOSE:To develop a semiconductor device with only one kind of design by equipping ROM in the same chip and by providing in the chip a circuit capable of selecting either ROM or an external memory for use. CONSTITUTION:A semiconductor device which includes ROM2 in its chip is provided with mode selection part 11 capable of setting selectively the 1st functional mode in which ROM2 is used for data processing and the 2nd functional mode in which an external memory is used. When selection part 11 selects mode I, gates 16 and 17 are opened in time-division mode and data are transferred, as shown in the table, between input data holding part 9 and output data holding part 10, and the outside. When selection part 11 selects mode II, on the other hand, the external memory is connected to time-division input-output terminal part 8 and gate 13 is opened in time-division mode to supply an address, generated at memory address part 1, to the external memory via terminal part 8; and data read out of the external memory enters data acceptance part 3 via gate 15 opened at the next timing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5605580A JPS56152060A (en) | 1980-04-26 | 1980-04-26 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5605580A JPS56152060A (en) | 1980-04-26 | 1980-04-26 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56152060A true JPS56152060A (en) | 1981-11-25 |
Family
ID=13016391
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5605580A Pending JPS56152060A (en) | 1980-04-26 | 1980-04-26 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56152060A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5943064U (en) * | 1982-09-14 | 1984-03-21 | スタンレー電気株式会社 | Mounting structure of the cap |
-
1980
- 1980-04-26 JP JP5605580A patent/JPS56152060A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5943064U (en) * | 1982-09-14 | 1984-03-21 | スタンレー電気株式会社 | Mounting structure of the cap |
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