JPS5394140A - Memory integrated circuit - Google Patents
Memory integrated circuitInfo
- Publication number
- JPS5394140A JPS5394140A JP769777A JP769777A JPS5394140A JP S5394140 A JPS5394140 A JP S5394140A JP 769777 A JP769777 A JP 769777A JP 769777 A JP769777 A JP 769777A JP S5394140 A JPS5394140 A JP S5394140A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- memory integrated
- circuit
- handing
- decrease
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
Landscapes
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To decrease the number of the lead wire for the memory integrated circuit, by handing the input/output signal, etc. of the memory integrated circuit in a serial way with the bit outside the circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP769777A JPS5394140A (en) | 1977-01-28 | 1977-01-28 | Memory integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP769777A JPS5394140A (en) | 1977-01-28 | 1977-01-28 | Memory integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5394140A true JPS5394140A (en) | 1978-08-17 |
Family
ID=11672951
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP769777A Pending JPS5394140A (en) | 1977-01-28 | 1977-01-28 | Memory integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5394140A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0152954A2 (en) * | 1984-02-21 | 1985-08-28 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
EP0179605A2 (en) * | 1984-10-17 | 1986-04-30 | Fujitsu Limited | Semiconductor memory device having a serial data input circuit and a serial data output circuit |
JPS61237287A (en) * | 1985-04-12 | 1986-10-22 | Mitsubishi Electric Corp | Semiconductor storage device |
JPS61237288A (en) * | 1985-04-15 | 1986-10-22 | Mitsubishi Electric Corp | Semiconductor storage device |
FR2591017A1 (en) * | 1985-11-29 | 1987-06-05 | Paris Laurent | Elementary shift register and shift registers comprising several elementary registers |
-
1977
- 1977-01-28 JP JP769777A patent/JPS5394140A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0152954A2 (en) * | 1984-02-21 | 1985-08-28 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US4715017A (en) * | 1984-02-21 | 1987-12-22 | Kabushiki Kaisha Toshiba | Semiconductor memory device with plural latches for read out |
EP0179605A2 (en) * | 1984-10-17 | 1986-04-30 | Fujitsu Limited | Semiconductor memory device having a serial data input circuit and a serial data output circuit |
JPS61237287A (en) * | 1985-04-12 | 1986-10-22 | Mitsubishi Electric Corp | Semiconductor storage device |
JPS61237288A (en) * | 1985-04-15 | 1986-10-22 | Mitsubishi Electric Corp | Semiconductor storage device |
FR2591017A1 (en) * | 1985-11-29 | 1987-06-05 | Paris Laurent | Elementary shift register and shift registers comprising several elementary registers |
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