JPS547248A - Signal process system - Google Patents

Signal process system

Info

Publication number
JPS547248A
JPS547248A JP7205377A JP7205377A JPS547248A JP S547248 A JPS547248 A JP S547248A JP 7205377 A JP7205377 A JP 7205377A JP 7205377 A JP7205377 A JP 7205377A JP S547248 A JPS547248 A JP S547248A
Authority
JP
Japan
Prior art keywords
process system
signal process
strobe signal
omission
minimize
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7205377A
Other languages
Japanese (ja)
Inventor
Hiroyuki Yoshimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7205377A priority Critical patent/JPS547248A/en
Publication of JPS547248A publication Critical patent/JPS547248A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To minimize the package size as well as to increase the packing density through omission of the corresponding input pin, by receiving the row strobe signal formed outside IC at the inside delay circuit and using this delay output as the line strobe signal.
JP7205377A 1977-06-20 1977-06-20 Signal process system Pending JPS547248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7205377A JPS547248A (en) 1977-06-20 1977-06-20 Signal process system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7205377A JPS547248A (en) 1977-06-20 1977-06-20 Signal process system

Related Child Applications (3)

Application Number Title Priority Date Filing Date
JP59104584A Division JPS6018893A (en) 1984-05-25 1984-05-25 Integrated circuit device
JP59104583A Division JPS6058551B2 (en) 1984-05-25 1984-05-25 integrated circuit memory device
JP59259150A Division JPS6049995B2 (en) 1984-12-10 1984-12-10 semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS547248A true JPS547248A (en) 1979-01-19

Family

ID=13478245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7205377A Pending JPS547248A (en) 1977-06-20 1977-06-20 Signal process system

Country Status (1)

Country Link
JP (1) JPS547248A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58130487A (en) * 1982-01-28 1983-08-03 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit
JPS5972050U (en) * 1982-11-05 1984-05-16 日立電子株式会社 transceiver
EP0137149A2 (en) * 1983-09-14 1985-04-17 International Business Machines Corporation A high speed memory accessing means and method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58130487A (en) * 1982-01-28 1983-08-03 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit
JPS5972050U (en) * 1982-11-05 1984-05-16 日立電子株式会社 transceiver
EP0137149A2 (en) * 1983-09-14 1985-04-17 International Business Machines Corporation A high speed memory accessing means and method

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