JPS5362949A - Input/output buffer circuit - Google Patents

Input/output buffer circuit

Info

Publication number
JPS5362949A
JPS5362949A JP13737376A JP13737376A JPS5362949A JP S5362949 A JPS5362949 A JP S5362949A JP 13737376 A JP13737376 A JP 13737376A JP 13737376 A JP13737376 A JP 13737376A JP S5362949 A JPS5362949 A JP S5362949A
Authority
JP
Japan
Prior art keywords
input
buffer circuit
output buffer
imedance
putting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13737376A
Other languages
Japanese (ja)
Inventor
Akiyoshi Kanuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13737376A priority Critical patent/JPS5362949A/en
Publication of JPS5362949A publication Critical patent/JPS5362949A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To avoid the electric short between the input/output buffers resulting from a timing discrepancy between the integrated circuits by putting the input/ output buffer circuit under a high imedance at least once at the former half part of the cycle time.
JP13737376A 1976-11-17 1976-11-17 Input/output buffer circuit Pending JPS5362949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13737376A JPS5362949A (en) 1976-11-17 1976-11-17 Input/output buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13737376A JPS5362949A (en) 1976-11-17 1976-11-17 Input/output buffer circuit

Publications (1)

Publication Number Publication Date
JPS5362949A true JPS5362949A (en) 1978-06-05

Family

ID=15197158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13737376A Pending JPS5362949A (en) 1976-11-17 1976-11-17 Input/output buffer circuit

Country Status (1)

Country Link
JP (1) JPS5362949A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5514744A (en) * 1978-07-17 1980-02-01 Nec Corp Output circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5514744A (en) * 1978-07-17 1980-02-01 Nec Corp Output circuit

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