JPS52146540A - Three-level memory circuit - Google Patents
Three-level memory circuitInfo
- Publication number
- JPS52146540A JPS52146540A JP6320276A JP6320276A JPS52146540A JP S52146540 A JPS52146540 A JP S52146540A JP 6320276 A JP6320276 A JP 6320276A JP 6320276 A JP6320276 A JP 6320276A JP S52146540 A JPS52146540 A JP S52146540A
- Authority
- JP
- Japan
- Prior art keywords
- memory circuit
- level memory
- constitution
- level
- circuit easily
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/29—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator multistable
Abstract
PURPOSE:To obtain a three-level memory circuit easily by relatively simplifying its constitution.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6320276A JPS52146540A (en) | 1976-05-31 | 1976-05-31 | Three-level memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6320276A JPS52146540A (en) | 1976-05-31 | 1976-05-31 | Three-level memory circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS52146540A true JPS52146540A (en) | 1977-12-06 |
Family
ID=13222378
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6320276A Pending JPS52146540A (en) | 1976-05-31 | 1976-05-31 | Three-level memory circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS52146540A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02104341U (en) * | 1989-02-07 | 1990-08-20 |
-
1976
- 1976-05-31 JP JP6320276A patent/JPS52146540A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02104341U (en) * | 1989-02-07 | 1990-08-20 |
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