JPS5449039A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS5449039A
JPS5449039A JP11625777A JP11625777A JPS5449039A JP S5449039 A JPS5449039 A JP S5449039A JP 11625777 A JP11625777 A JP 11625777A JP 11625777 A JP11625777 A JP 11625777A JP S5449039 A JPS5449039 A JP S5449039A
Authority
JP
Japan
Prior art keywords
terminal
input signal
logic circuit
nand6
nor7
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11625777A
Other languages
Japanese (ja)
Inventor
Keiji Kawabata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11625777A priority Critical patent/JPS5449039A/en
Publication of JPS5449039A publication Critical patent/JPS5449039A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits

Abstract

PURPOSE:To reduce the chip size of a logic circuit with an AND/OR function by eliminating the need of an AND-NOR circuit only by adding two set/reset MOS transistors. CONSTITUTION:To function to operate OR, input terminals T5 and T6 are supplied with [1]. At this time, if the input signal to data input terminal T1 is [1], outputs of NAND6 and NOR7 are both [0], so that Q5 and Q8 will turn ON and OFF respectively. Supplying [1] to control terminal T2 causes inverter IV1 to output [1]. In addition, supplying input signal [0] to terminal T1 causes NAND6 and NOR7 to output signals [1] and [0], and Q5 and Q8 both turn OFF, so that IVs 1 and 2 will remain in the data holding states and the output signal will not change if the input signal to terminal T2 turns into [1]. That results in that the AND/OR operation has been achieved.
JP11625777A 1977-09-27 1977-09-27 Logic circuit Pending JPS5449039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11625777A JPS5449039A (en) 1977-09-27 1977-09-27 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11625777A JPS5449039A (en) 1977-09-27 1977-09-27 Logic circuit

Publications (1)

Publication Number Publication Date
JPS5449039A true JPS5449039A (en) 1979-04-18

Family

ID=14682625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11625777A Pending JPS5449039A (en) 1977-09-27 1977-09-27 Logic circuit

Country Status (1)

Country Link
JP (1) JPS5449039A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010910A (en) * 1983-06-30 1985-01-21 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Latch circuit array
US4779010A (en) * 1986-07-29 1988-10-18 Advanced Micro Devices, Inc. Monostable logic gate in a programmable logic array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010910A (en) * 1983-06-30 1985-01-21 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Latch circuit array
US4779010A (en) * 1986-07-29 1988-10-18 Advanced Micro Devices, Inc. Monostable logic gate in a programmable logic array

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