JPS5493343A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5493343A
JPS5493343A JP15844877A JP15844877A JPS5493343A JP S5493343 A JPS5493343 A JP S5493343A JP 15844877 A JP15844877 A JP 15844877A JP 15844877 A JP15844877 A JP 15844877A JP S5493343 A JPS5493343 A JP S5493343A
Authority
JP
Japan
Prior art keywords
circuit
output
power supply
semiconductor integrated
given value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15844877A
Other languages
Japanese (ja)
Inventor
Yasunori Kanai
Kazuyasu Ejiri
Hiroshi Yoshikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15844877A priority Critical patent/JPS5493343A/en
Publication of JPS5493343A publication Critical patent/JPS5493343A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection

Landscapes

  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

PURPOSE:To avoid the destruction of the output circuit, by holding the output terminal of the logic circuit at high impedance with the output signal of the voltage detection circuit outputting signal when the power supply voltage reaches a given value, in tristate output type semiconductor integrated circuit. CONSTITUTION:The tristate control circuit 1 is connected to the tristate output type semiconductor integrated circuits 31,32...3n, and the integrated circuits 31,31...3n are connected to the bus line 2. Further, every integrated circuit is provided with the power supply detection circuit 6 outputting singal when the power supply voltage Vcc reaches a given value, and the output of the detection circuit 6 is fed to another input of the NOT sum circuit feeding the output of the control circuit 1 to one input, the inverter 4 is controlled with the output signal of the circuit 5, holding the output of the integrated circuits 31,32...3n to a high impedance until the power supply voltage Vcc reaches a given value.
JP15844877A 1977-12-30 1977-12-30 Semiconductor integrated circuit Pending JPS5493343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15844877A JPS5493343A (en) 1977-12-30 1977-12-30 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15844877A JPS5493343A (en) 1977-12-30 1977-12-30 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5493343A true JPS5493343A (en) 1979-07-24

Family

ID=15671970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15844877A Pending JPS5493343A (en) 1977-12-30 1977-12-30 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5493343A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5949620A (en) * 1982-08-02 1984-03-22 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Power source threshold activation circuit
JPS5952920A (en) * 1982-08-16 1984-03-27 アナログ　デバイセス　インコ−ポレ−テツド 3-state type output buffer
JPS6462020A (en) * 1987-09-01 1989-03-08 Fujitsu Ltd Gate array

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5027466A (en) * 1973-07-10 1975-03-20

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5027466A (en) * 1973-07-10 1975-03-20

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5949620A (en) * 1982-08-02 1984-03-22 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Power source threshold activation circuit
JPS5952920A (en) * 1982-08-16 1984-03-27 アナログ　デバイセス　インコ−ポレ−テツド 3-state type output buffer
JPS6462020A (en) * 1987-09-01 1989-03-08 Fujitsu Ltd Gate array

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