JPS5691536A - Multiple-valued level output circuit - Google Patents

Multiple-valued level output circuit

Info

Publication number
JPS5691536A
JPS5691536A JP16975679A JP16975679A JPS5691536A JP S5691536 A JPS5691536 A JP S5691536A JP 16975679 A JP16975679 A JP 16975679A JP 16975679 A JP16975679 A JP 16975679A JP S5691536 A JPS5691536 A JP S5691536A
Authority
JP
Japan
Prior art keywords
level
control signal
mos transistors
inverters
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16975679A
Other languages
Japanese (ja)
Inventor
Toshio Yuyama
Ryuzo Shiraki
Seiji Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16975679A priority Critical patent/JPS5691536A/en
Priority to US06/216,818 priority patent/US4408135A/en
Priority to EP80108142A priority patent/EP0031582A1/en
Publication of JPS5691536A publication Critical patent/JPS5691536A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent a latch-up state and the destruction of an element by mutually connecting output terminals of a couple of inverters differing in power voltage and by turning on and off those inverters through complementary switching. CONSTITUTION:As the 1st control signal is helt at level [L], inverters composed of MOS transistors T1 and T2 are turned on to generate outputs of levels VDD1 and VSS1 obtained by inverting the input. When the 1st control signal is held at level [H], MOS transistors T1 and T2 are turned off regardless of the input and the inverter outputs are in high impedance state. In response to the 2nd control signal, the same operation is performed to hold outputs of MOS transistors T3 and T4 at VDD2 and VSS2. The 1st and 2nd control signals are both inhibited from being at level [L].
JP16975679A 1979-12-26 1979-12-26 Multiple-valued level output circuit Pending JPS5691536A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP16975679A JPS5691536A (en) 1979-12-26 1979-12-26 Multiple-valued level output circuit
US06/216,818 US4408135A (en) 1979-12-26 1980-12-16 Multi-level signal generating circuit
EP80108142A EP0031582A1 (en) 1979-12-26 1980-12-22 Multi-level signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16975679A JPS5691536A (en) 1979-12-26 1979-12-26 Multiple-valued level output circuit

Publications (1)

Publication Number Publication Date
JPS5691536A true JPS5691536A (en) 1981-07-24

Family

ID=15892258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16975679A Pending JPS5691536A (en) 1979-12-26 1979-12-26 Multiple-valued level output circuit

Country Status (1)

Country Link
JP (1) JPS5691536A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59165045U (en) * 1983-04-19 1984-11-06 日本電気株式会社 microcomputer
JPH01190024A (en) * 1988-01-25 1989-07-31 Mitsubishi Electric Corp Trigger circuit for control rectifier element
US6486697B1 (en) * 1999-03-22 2002-11-26 University Of Southern California Line reflection reduction with energy-recovery driver

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59165045U (en) * 1983-04-19 1984-11-06 日本電気株式会社 microcomputer
JPS6324502Y2 (en) * 1983-04-19 1988-07-05
JPH01190024A (en) * 1988-01-25 1989-07-31 Mitsubishi Electric Corp Trigger circuit for control rectifier element
US6486697B1 (en) * 1999-03-22 2002-11-26 University Of Southern California Line reflection reduction with energy-recovery driver
US6946868B2 (en) 1999-03-22 2005-09-20 University Of Southern California Line reflection reduction with energy-recovery driver
US7176712B2 (en) 1999-03-22 2007-02-13 University Of Southern California Line reflection reduction with energy-recovery driver
US7504852B2 (en) 1999-03-22 2009-03-17 University Of Southern California Line reflection reduction with energy-recovery driver

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