JPS6324502Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a microcomputer, and particularly to its output circuit.

Microcomputers use LSIs to integrate each circuit.
It is common to use a tester to test the internal circuit operation of a one-chip microcomputer that has built-in memory (ROM). In particular, in the case of a one-chip microcomputer with built-in memory (ROM), a command code is input from the tester through an external terminal, and the state after the command is executed is output from the external terminal to test the internal circuit operation. Therefore, in the past, after testing a command, the internal state of the one-chip microcomputer (i.e., the test result) was always checked to confirm whether the command was executed correctly.
To this end, it was necessary to execute an output command for each test, which instructs the output of the test pattern to an external terminal, and this resulted in tests taking a long time using a very long test pattern.

An object of the present invention is to provide a microcomputer that can output the internal state of the microcomputer after executing an instruction to the outside without using an output instruction.

The present invention is characterized in that the final stage transistor in the output circuit of the microcomputer is capable of generating output signals of at least three levels in response to a combination of a plurality of signals.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a functional block diagram of a one-chip microcomputer according to an embodiment of the present invention, which includes a CPU circuit section 1, a ROM circuit section 2,
It consists of a RAM circuit section 3 and an output circuit section 4, which are interconnected by an internal data bus 5. In FIG. 1, all data output to the outside is outputted from the output circuit section 4 through the internal data bus 5. Output terminals corresponding to the number of output data bits are connected to the output circuit section 4.

The circuit diagram of FIG. 2 shows a part (one bit) of the output circuit 4 of FIG. The output final stage MOS transistors 11, 12, and 13 are connected to each other as shown in the figure, and a common output point is connected to the external output terminal 8. The MOS transistor 11 receives the input signal 6 to the output circuit at its gate, and similarly
Transistor 12 is connected to receive input signal 7 to the output circuit at its gate. Also, MOS
A MOS transistor 13 connected in series with the transistor 11 is configured to receive the input signal 6 via an inverter 14.

FIG. 3 shows an output waveform diagram of the output circuit of FIG. 2. V ₁ , V ₂ , and V ₃ in FIG. 3 each indicate the output level of the output waveform, and the relationship is V ₁ <V ₂ <V ₃ . The operation of FIG. 2 will be explained with reference to FIG. 3.
In FIG. 2, when the input signals 7 and 6 to the output circuit are both low level, the MOS transistors 11 and 1
2 is in the OFF state, the MOS transistor 13 is in the ON state, and the _V1 level in Fig. 3 is the external output terminal 8.
is output to. Next, when the output circuit input signal 6 changes to a high level, the MOS transistor 13 turns OFF.
MOS transistor 11 turns on and external resistance (load)
9, and the V ₂ level shown in FIG. 3 appears at the external output terminal 8. Next, when the input signal 6 to the output circuit is high level and the input signal 7 to the output circuit is high level, MOS transistors 11 and 12 are turned on simultaneously.
Therefore, a V ₃ level higher than V ₂ in FIG. 3 is output to the external output terminal 8. Therefore, by detecting the output level of output terminal 8 with an LSI tester,
Due to the difference in their levels, it is possible to take out a plurality of signals to the outside and inspect them using a single external terminal.

Therefore, in the embodiment of the present invention, the input signal 6 to the output circuit is set to the signal during normal operation of the microcomputer, and the _V1 level is set to be below the output low level standard, and the _V2 level is set to be above the output high level standard. By doing so, it is possible to normally output the signal as the normal output of the one-chip microcomputer, regardless of the state of the input signal 7 to the output circuit. Also, by connecting the gate of the transistor 12 that receives the input signal 7 to the output circuit to a specific circuit section in the internal circuit of the one-chip microcomputer,
The state of a specific circuit section can be tested continuously during testing with an LSI tester.

In other words, the state of a specific circuit section can be directly tested based on differences in output levels without executing conventional output commands. Therefore, a 1-chip microcomputer can be efficiently tested with a short test pattern.

This idea has been explained using a one-chip microcomputer as an example, but it consists of configuring the internal output stage transistors so that multiple levels can be output to one output terminal, and all other transistor circuits It is clear that it can also be applied to

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of a one-chip microcomputer according to an embodiment of the present invention, and FIG. 2 is a partial circuit configuration diagram of the output circuit section shown in FIG. 1.
FIG. 3 is an output waveform diagram of the output circuit section of FIG. 2. 1...CPU circuit section, 2...ROM circuit section, 3...
...RAM circuit section, 4...Output circuit section, 5...Internal data bus, 6, 7...Output circuit input signal, 8...
...External output terminal, 9...External resistance, 11, 12,
13...MOS transistor, 14...inverter.

Claims (1)

[Scope of utility model registration request] first and second field effect transistors connected in parallel between the first power supply terminal and the output terminal; and a third field effect transistor connected between the output terminal and the second power supply terminal. and control means for making one of the first and third transistors conductive and the other non-conductive in response to an internal signal generated based on the normal operation of the microcomputer;
means for controlling conduction of the second transistor by a signal output from a specific circuit within the microcomputer during testing;
and a resistance means connected between a power terminal of the microcomputer and a power terminal of the microcomputer.