JPS55147039A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS55147039A
JPS55147039A JP5672379A JP5672379A JPS55147039A JP S55147039 A JPS55147039 A JP S55147039A JP 5672379 A JP5672379 A JP 5672379A JP 5672379 A JP5672379 A JP 5672379A JP S55147039 A JPS55147039 A JP S55147039A
Authority
JP
Japan
Prior art keywords
input
logic circuit
level
binary
ternary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5672379A
Other languages
Japanese (ja)
Inventor
Toru Kuwabara
Hisayoshi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5672379A priority Critical patent/JPS55147039A/en
Publication of JPS55147039A publication Critical patent/JPS55147039A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0002—Multistate logic

Abstract

PURPOSE:To reduce the number of input lines, by connecting the ternary input logic circuit which outputs two binary level signals to the input of the binary logic circuit. CONSTITUTION:The ternary input logic circuit 4 is connected to the binary logic circuit 1. The circuit 4 is constituted by commonly connecting the input of the inverters A, B different in transit voltage each other. H level, L level and M level which is intermediate to them are used for the control input 5. If the transition voltage of the inverter B is smaller than that of the inverter A, the ternary levels of H, L, M given to one input line are fed to the output terminals C, D and the outputs of the binary level of (L,L), (H,H), (H,L) are fed to the circuit 1 respectively. Accordingly, the number of input lines can be decreased by one.
JP5672379A 1979-05-04 1979-05-04 Logic circuit Pending JPS55147039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5672379A JPS55147039A (en) 1979-05-04 1979-05-04 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5672379A JPS55147039A (en) 1979-05-04 1979-05-04 Logic circuit

Publications (1)

Publication Number Publication Date
JPS55147039A true JPS55147039A (en) 1980-11-15

Family

ID=13035402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5672379A Pending JPS55147039A (en) 1979-05-04 1979-05-04 Logic circuit

Country Status (1)

Country Link
JP (1) JPS55147039A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57138220A (en) * 1981-02-20 1982-08-26 Hitachi Ltd Data input equipment for logical circuit
EP0589221A1 (en) * 1992-09-24 1994-03-30 Siemens Aktiengesellschaft Semiconductor integrated circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57138220A (en) * 1981-02-20 1982-08-26 Hitachi Ltd Data input equipment for logical circuit
JPH0257377B2 (en) * 1981-02-20 1990-12-04 Hitachi Ltd
EP0589221A1 (en) * 1992-09-24 1994-03-30 Siemens Aktiengesellschaft Semiconductor integrated circuit device

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