JPS54124664A - Integrated circuit unit - Google Patents

Integrated circuit unit

Info

Publication number
JPS54124664A
JPS54124664A JP3269978A JP3269978A JPS54124664A JP S54124664 A JPS54124664 A JP S54124664A JP 3269978 A JP3269978 A JP 3269978A JP 3269978 A JP3269978 A JP 3269978A JP S54124664 A JPS54124664 A JP S54124664A
Authority
JP
Japan
Prior art keywords
gate
terminal
bit
output
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3269978A
Other languages
Japanese (ja)
Inventor
Hiromichi Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3269978A priority Critical patent/JPS54124664A/en
Publication of JPS54124664A publication Critical patent/JPS54124664A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio

Abstract

PURPOSE:To reduce the number of output terminals by adding a control circuits, by which true or false binary output is obtained, to the same output terminal in the integrated circuit having the logical function for plural bits. CONSTITUTION:One output terminal Ni is provided for every bit, and a T/C terminal which controls true and false outputs is added in stead of the other output terminal. When a logical ''1'' state is applied to the T/C terminal, gate 2 of every bit does not change the output in any state of input terminal Ii, and every bit has a logic from gate 1 through gate 3. Reversely, when a logical ''0'' state is applied to the T/C terminal, gate 1 of every bit has the state fixed, and every bit has a logic from gate 2 through gate 3.
JP3269978A 1978-03-20 1978-03-20 Integrated circuit unit Pending JPS54124664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3269978A JPS54124664A (en) 1978-03-20 1978-03-20 Integrated circuit unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3269978A JPS54124664A (en) 1978-03-20 1978-03-20 Integrated circuit unit

Publications (1)

Publication Number Publication Date
JPS54124664A true JPS54124664A (en) 1979-09-27

Family

ID=12366089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3269978A Pending JPS54124664A (en) 1978-03-20 1978-03-20 Integrated circuit unit

Country Status (1)

Country Link
JP (1) JPS54124664A (en)

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