JPS57129536A - Variable logic device - Google Patents

Variable logic device

Info

Publication number
JPS57129536A
JPS57129536A JP56015384A JP1538481A JPS57129536A JP S57129536 A JPS57129536 A JP S57129536A JP 56015384 A JP56015384 A JP 56015384A JP 1538481 A JP1538481 A JP 1538481A JP S57129536 A JPS57129536 A JP S57129536A
Authority
JP
Japan
Prior art keywords
cell
logic
writing
gate switch
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56015384A
Other languages
Japanese (ja)
Inventor
Tsutomu Komatsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56015384A priority Critical patent/JPS57129536A/en
Publication of JPS57129536A publication Critical patent/JPS57129536A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters

Abstract

PURPOSE:To ensure a free correction for an overall logic, by varying the connection between the minimum elements that realizes a logic. CONSTITUTION:A tristate buffer 12 is made conductive and nonconductive by writing ''1'' or ''0'' into a register 11 through a writing line 13 from the outside. Thus the ON/OFF is controlled for a corresponding gate switch. For instance, when a cell 1 secures an NOR logic to the values of signal input lines 2 and 3 to deliver it to a signal output line 4, gate switches 5, 6 and 7 are turned on. While a gate switch 9 is closed in case the cell 1 is used just as a wiring route for the lines 3 and 4. In such a way, a wiring state or a logical operation state is set to each cell to realize a logical connection for an optional logical circuit.
JP56015384A 1981-02-04 1981-02-04 Variable logic device Pending JPS57129536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56015384A JPS57129536A (en) 1981-02-04 1981-02-04 Variable logic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56015384A JPS57129536A (en) 1981-02-04 1981-02-04 Variable logic device

Publications (1)

Publication Number Publication Date
JPS57129536A true JPS57129536A (en) 1982-08-11

Family

ID=11887249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56015384A Pending JPS57129536A (en) 1981-02-04 1981-02-04 Variable logic device

Country Status (1)

Country Link
JP (1) JPS57129536A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119925A (en) * 1982-12-27 1984-07-11 Toshiba Corp Logical circuit
JPS62115844A (en) * 1985-09-11 1987-05-27 ピルキントン　マイクロ−エレクトロニクス　リミテツド Semiconductor integrated circuit and system
WO1991001840A1 (en) * 1989-07-26 1991-02-21 Sodick Co., Ltd. Pulse controller of electric discharge machine
JPH03204957A (en) * 1990-08-31 1991-09-06 Toshiba Corp Semiconductor integrated circuit
US5182474A (en) * 1991-03-26 1993-01-26 Sodick Co., Ltd. Pulse control circuit for electric discharge machine using programmable logic
JPH06318637A (en) * 1993-11-01 1994-11-15 Toshiba Corp Semiconductor integrated circuit
USRE35125E (en) * 1989-07-26 1995-12-19 Sodick Co., Ltd. Pulse control circuit for electric discharge machine using programmable logic
JP2869549B2 (en) * 1989-07-26 1999-03-10 株式会社ソディック Pulse control device for electric discharge machine
US6356109B1 (en) 1999-02-10 2002-03-12 Nec Corporation Programmable device
US6424171B1 (en) 1998-10-30 2002-07-23 Nec Corporation Base cell and two-dimensional array of base cells for programmable logic LSI

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119925A (en) * 1982-12-27 1984-07-11 Toshiba Corp Logical circuit
JPS62115844A (en) * 1985-09-11 1987-05-27 ピルキントン　マイクロ−エレクトロニクス　リミテツド Semiconductor integrated circuit and system
WO1991001840A1 (en) * 1989-07-26 1991-02-21 Sodick Co., Ltd. Pulse controller of electric discharge machine
USRE35125E (en) * 1989-07-26 1995-12-19 Sodick Co., Ltd. Pulse control circuit for electric discharge machine using programmable logic
JP2869549B2 (en) * 1989-07-26 1999-03-10 株式会社ソディック Pulse control device for electric discharge machine
JPH03204957A (en) * 1990-08-31 1991-09-06 Toshiba Corp Semiconductor integrated circuit
US5182474A (en) * 1991-03-26 1993-01-26 Sodick Co., Ltd. Pulse control circuit for electric discharge machine using programmable logic
JPH06318637A (en) * 1993-11-01 1994-11-15 Toshiba Corp Semiconductor integrated circuit
US6424171B1 (en) 1998-10-30 2002-07-23 Nec Corporation Base cell and two-dimensional array of base cells for programmable logic LSI
US6356109B1 (en) 1999-02-10 2002-03-12 Nec Corporation Programmable device

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