JPS57191746A - Input and output device - Google Patents

Input and output device

Info

Publication number
JPS57191746A
JPS57191746A JP56075157A JP7515781A JPS57191746A JP S57191746 A JPS57191746 A JP S57191746A JP 56075157 A JP56075157 A JP 56075157A JP 7515781 A JP7515781 A JP 7515781A JP S57191746 A JPS57191746 A JP S57191746A
Authority
JP
Japan
Prior art keywords
shift register
input
cpu4
output
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56075157A
Other languages
Japanese (ja)
Inventor
Tadashi Nishijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56075157A priority Critical patent/JPS57191746A/en
Publication of JPS57191746A publication Critical patent/JPS57191746A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00Parallel/series conversion or vice versa

Abstract

PURPOSE:To simplify the constitution, by switching selectively a switch circuit, which switches the mode to the input mode and the output mode, to switch and use a single shift register for the input and the output. CONSTITUTION:A shift register 10 and a latch 7, to which the load pulse outputted from a CPU4 is given, of an input/output device which transmits and receives data signals in serial to and from the CPU4 are switched selectively by a switch circuit 11. When a load pulse PS from the CPU4 is given to the shift register 10, the shift register 10 fetches external input data. When the load pulse PS from the CPU4 is given to the latch 7, the latch 7 fetches contents of the shift register 10 and holds them. Thus, the shift register 10 is switched and used for the input and output by the selective switching of the switch circuit 11.
JP56075157A 1981-05-19 1981-05-19 Input and output device Pending JPS57191746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56075157A JPS57191746A (en) 1981-05-19 1981-05-19 Input and output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56075157A JPS57191746A (en) 1981-05-19 1981-05-19 Input and output device

Publications (1)

Publication Number Publication Date
JPS57191746A true JPS57191746A (en) 1982-11-25

Family

ID=13568083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56075157A Pending JPS57191746A (en) 1981-05-19 1981-05-19 Input and output device

Country Status (1)

Country Link
JP (1) JPS57191746A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62233931A (en) * 1986-04-03 1987-10-14 Fujitsu Ten Ltd Parallel serial converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62233931A (en) * 1986-04-03 1987-10-14 Fujitsu Ten Ltd Parallel serial converter
JPH0370415B2 (en) * 1986-04-03 1991-11-07 Fujitsu Ten Ltd

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