JPS5680718A - Oscillation prevention system - Google Patents

Oscillation prevention system

Info

Publication number
JPS5680718A
JPS5680718A JP15786079A JP15786079A JPS5680718A JP S5680718 A JPS5680718 A JP S5680718A JP 15786079 A JP15786079 A JP 15786079A JP 15786079 A JP15786079 A JP 15786079A JP S5680718 A JPS5680718 A JP S5680718A
Authority
JP
Japan
Prior art keywords
output
flip
maintenance
signal
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15786079A
Other languages
Japanese (ja)
Inventor
Kazeo Sugiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15786079A priority Critical patent/JPS5680718A/en
Publication of JPS5680718A publication Critical patent/JPS5680718A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent a maintenance operating circuit from oscillating by controlling two outputs regarding a maintenance operation signal so that one output of them is delayed.
CONSTITUTION: Control signal C is obtained by operating flip-flop 3 via an adapter device and inverters 1 and 2 either by switching switch SW of a maintenance panel or with remote switch signal (RSW). Between flip-flop FFO of the adapter device and drivers 13 and 14, a delaying circuit consisting of counter 12, flip-flop circuits FF1 and FF2, and OR circuits OR1WOR3 is provided. When the output of FF0 is inverted through the operation of the maintenance panel or inversion of signal RSW, output (a) or (b) of driver 13 or 14 is delayed by the output of the delaying circuit, and consequently both inputs J and K of JKFF3 are never held at "0" or "1" at the same time, preventing oscillation.
COPYRIGHT: (C)1981,JPO&Japio
JP15786079A 1979-12-05 1979-12-05 Oscillation prevention system Pending JPS5680718A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15786079A JPS5680718A (en) 1979-12-05 1979-12-05 Oscillation prevention system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15786079A JPS5680718A (en) 1979-12-05 1979-12-05 Oscillation prevention system

Publications (1)

Publication Number Publication Date
JPS5680718A true JPS5680718A (en) 1981-07-02

Family

ID=15658959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15786079A Pending JPS5680718A (en) 1979-12-05 1979-12-05 Oscillation prevention system

Country Status (1)

Country Link
JP (1) JPS5680718A (en)

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