JPS56137422A - Input and output controlling system - Google Patents

Input and output controlling system

Info

Publication number
JPS56137422A
JPS56137422A JP4172680A JP4172680A JPS56137422A JP S56137422 A JPS56137422 A JP S56137422A JP 4172680 A JP4172680 A JP 4172680A JP 4172680 A JP4172680 A JP 4172680A JP S56137422 A JPS56137422 A JP S56137422A
Authority
JP
Japan
Prior art keywords
input
signal
circuit
output
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4172680A
Other languages
Japanese (ja)
Inventor
Kiyoo Moroto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4172680A priority Critical patent/JPS56137422A/en
Publication of JPS56137422A publication Critical patent/JPS56137422A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To prevent the switching of analog interface due to failure in the input and output device, by switching the analog interface with the device selecting signal from the upper-rank device, in the analog interface switch for magnetic tape device or the like. CONSTITUTION:The device selecting instruction and the device number fed from the upper-rank device are respectively received at the tag decoding circuit 14 and the address decoding circuit 15. The circuit 14 inputs the production of the device selecting instruction to the AND circuits 16, 17 via the signal 19, and the circuit 15 inputs the signal indicating the input/output device 2 on the signal line 20 and the signal indicating the input/output device 3 on the signal line 21, respectively to the circuits 16 and 17. Thus, the signal corresponding to the devices 2, 3 is outputted from the circuits 16, 17 and set to the latch circuit 18. The output of the circuit 18 switches the analog switch 13 at the input/output devices 2, 3 corresponding via the signal line 22.
JP4172680A 1980-03-31 1980-03-31 Input and output controlling system Pending JPS56137422A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4172680A JPS56137422A (en) 1980-03-31 1980-03-31 Input and output controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4172680A JPS56137422A (en) 1980-03-31 1980-03-31 Input and output controlling system

Publications (1)

Publication Number Publication Date
JPS56137422A true JPS56137422A (en) 1981-10-27

Family

ID=12616419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4172680A Pending JPS56137422A (en) 1980-03-31 1980-03-31 Input and output controlling system

Country Status (1)

Country Link
JP (1) JPS56137422A (en)

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