JPS57150023A - Preventing device for simultaneous push of plural keys - Google Patents

Preventing device for simultaneous push of plural keys

Info

Publication number
JPS57150023A
JPS57150023A JP56034919A JP3491981A JPS57150023A JP S57150023 A JPS57150023 A JP S57150023A JP 56034919 A JP56034919 A JP 56034919A JP 3491981 A JP3491981 A JP 3491981A JP S57150023 A JPS57150023 A JP S57150023A
Authority
JP
Japan
Prior art keywords
circuit
inverter
keys
signal
inverted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56034919A
Other languages
Japanese (ja)
Inventor
Tetsuo Kishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP56034919A priority Critical patent/JPS57150023A/en
Publication of JPS57150023A publication Critical patent/JPS57150023A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
    • H03M11/02—Details

Abstract

PURPOSE:To prevent the malfunction caused by simultaneous pushing of plural keys, by using a simple logical circuit comprising an AND circuit, an OR circuit and an inverter. CONSTITUTION:An AND circuit 3 and an OR circuit 4 are connected in parallel to the branch points between keys 1, 2 and resistances 5, 6, and the signal given from the circuit 4 is inverted by an inverte 7. The output signals given from the inverter 7 and the circuit 3 are put together via diodes 9 and 10 and then inverted by an inverter 8. A switching element 11 is turned on and off by the output of the inverter 8. In case both keys 1 and 2 are erroneously pushed at one time, the signal voltage is applied to both input terminals 19 and 23 of the circuit 3. Then an output H signal is delivered from the circuit 3 and inverted to signal L by the inverter 8 to turn off the element 11.
JP56034919A 1981-03-10 1981-03-10 Preventing device for simultaneous push of plural keys Pending JPS57150023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56034919A JPS57150023A (en) 1981-03-10 1981-03-10 Preventing device for simultaneous push of plural keys

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56034919A JPS57150023A (en) 1981-03-10 1981-03-10 Preventing device for simultaneous push of plural keys

Publications (1)

Publication Number Publication Date
JPS57150023A true JPS57150023A (en) 1982-09-16

Family

ID=12427618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56034919A Pending JPS57150023A (en) 1981-03-10 1981-03-10 Preventing device for simultaneous push of plural keys

Country Status (1)

Country Link
JP (1) JPS57150023A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5154332A (en) * 1974-11-07 1976-05-13 Tokyo Electric Co Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5154332A (en) * 1974-11-07 1976-05-13 Tokyo Electric Co Ltd

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