JPS57164334A - Operating device - Google Patents

Operating device

Info

Publication number
JPS57164334A
JPS57164334A JP56049753A JP4975381A JPS57164334A JP S57164334 A JPS57164334 A JP S57164334A JP 56049753 A JP56049753 A JP 56049753A JP 4975381 A JP4975381 A JP 4975381A JP S57164334 A JPS57164334 A JP S57164334A
Authority
JP
Japan
Prior art keywords
bit
carry
alu
turns
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56049753A
Other languages
Japanese (ja)
Other versions
JPS622328B2 (en
Inventor
Tomoaki Isozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56049753A priority Critical patent/JPS57164334A/en
Publication of JPS57164334A publication Critical patent/JPS57164334A/en
Publication of JPS622328B2 publication Critical patent/JPS622328B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To simply execute many kinds of multiple notation operation, by inhibiting or enabling a carry signal from an arbitrary bit. CONSTITUTION:Circuits 1-8 are arithmetic logical operation circuits in 1 bit. When the input of the 1st signal terminal 32 goes to ''1'', an output of inverters 9 and 10 goes to ''0'', a transfer gate 13 turns off and a transfer gate 14 turns on, and a carry input of an ALU7 is always at ''0''. Thus, no carry from an ALU 6 to the ALU7 enters and the carry output of the ALU 6 is outputted to the 2nd signal terminal 33 because a gate 12 turns on. Thus, when an operation is made at this state, the carry from the 6-th bit to the 7-th bit is inhibited and if there exists a carry from the 6-th bit to the 7-th bit, this signal is outputted to the terminal 33. Then, the function of a 8-bit ALU and that of a 6-bit ALU can be switched according to the objective.
JP56049753A 1981-04-02 1981-04-02 Operating device Granted JPS57164334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56049753A JPS57164334A (en) 1981-04-02 1981-04-02 Operating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56049753A JPS57164334A (en) 1981-04-02 1981-04-02 Operating device

Publications (2)

Publication Number Publication Date
JPS57164334A true JPS57164334A (en) 1982-10-08
JPS622328B2 JPS622328B2 (en) 1987-01-19

Family

ID=12839937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56049753A Granted JPS57164334A (en) 1981-04-02 1981-04-02 Operating device

Country Status (1)

Country Link
JP (1) JPS57164334A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0376186A2 (en) * 1988-12-27 1990-07-04 Nec Corporation Method of controlling arithmetic pipeline configuration in multiprocessor system
EP0464601A2 (en) * 1990-06-25 1992-01-08 Nec Corporation Arithmetic operation system
US5109480A (en) * 1988-12-20 1992-04-28 Hitachi, Ltd. Drawing processor including arithmetical unit for improved superposed picture display
EP0486143A2 (en) * 1990-11-15 1992-05-20 International Business Machines Corporation Parallel processing of data
WO2018116483A1 (en) * 2016-12-21 2018-06-28 和己 阿部 Calculation using numerical values represented inside a computer in undecimal or higher positional notation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5563434A (en) * 1978-11-07 1980-05-13 Fujitsu Ltd Adder

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5563434A (en) * 1978-11-07 1980-05-13 Fujitsu Ltd Adder

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5109480A (en) * 1988-12-20 1992-04-28 Hitachi, Ltd. Drawing processor including arithmetical unit for improved superposed picture display
EP0376186A2 (en) * 1988-12-27 1990-07-04 Nec Corporation Method of controlling arithmetic pipeline configuration in multiprocessor system
EP0464601A2 (en) * 1990-06-25 1992-01-08 Nec Corporation Arithmetic operation system
EP0486143A2 (en) * 1990-11-15 1992-05-20 International Business Machines Corporation Parallel processing of data
EP0486143A3 (en) * 1990-11-15 1993-03-24 International Business Machines Corporation Parallel processing of data
US5909552A (en) * 1990-11-15 1999-06-01 International Business Machines Corporation Method and apparatus for processing packed data
WO2018116483A1 (en) * 2016-12-21 2018-06-28 和己 阿部 Calculation using numerical values represented inside a computer in undecimal or higher positional notation

Also Published As

Publication number Publication date
JPS622328B2 (en) 1987-01-19

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