JPS6413808A - Latching circuit - Google Patents
Latching circuitInfo
- Publication number
- JPS6413808A JPS6413808A JP62168752A JP16875287A JPS6413808A JP S6413808 A JPS6413808 A JP S6413808A JP 62168752 A JP62168752 A JP 62168752A JP 16875287 A JP16875287 A JP 16875287A JP S6413808 A JPS6413808 A JP S6413808A
- Authority
- JP
- Japan
- Prior art keywords
- output
- terminal
- signal
- data signal
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To attain how to use of latching a data signal separately by providing a circuit selecting by which of a level of a clock signal or an edge of the clock signal a data signal is to be fetched to a gate circuit of the latching circuit. CONSTITUTION:In applying a control signal 0 to a clock signal control terminal 14, when the clock signal level fed to a clock input terminal 2 changes from 0 to 1, an output of a NOT 5 goes to 0. Thus, outputs of ORs 12, 13 are respectively the same as the output of a NAND 8 and the output of a NOT 6 being its inverted output and the data signal fed to a terminal 1 is fetched by a latching part composed of NANDs 9, 10. On the other hand, in applying a control signal 1 to the terminal 14, when the clock signal fed to the terminal 2 is logic 1, the outputs of the ORs 12, 13 are respectively the data signal and the output of the NOT 6 being its inverted output and the data signal is fetched in the latching part.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62168752A JPS6413808A (en) | 1987-07-08 | 1987-07-08 | Latching circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62168752A JPS6413808A (en) | 1987-07-08 | 1987-07-08 | Latching circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6413808A true JPS6413808A (en) | 1989-01-18 |
Family
ID=15873773
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62168752A Pending JPS6413808A (en) | 1987-07-08 | 1987-07-08 | Latching circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6413808A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6249163B1 (en) * | 1995-11-16 | 2001-06-19 | Matra Bae Dynamics (Uk) Limited | Logic circuits |
-
1987
- 1987-07-08 JP JP62168752A patent/JPS6413808A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6249163B1 (en) * | 1995-11-16 | 2001-06-19 | Matra Bae Dynamics (Uk) Limited | Logic circuits |
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