JPS56110130A - Priority concurrent circuit - Google Patents

Priority concurrent circuit

Info

Publication number
JPS56110130A
JPS56110130A JP1336680A JP1336680A JPS56110130A JP S56110130 A JPS56110130 A JP S56110130A JP 1336680 A JP1336680 A JP 1336680A JP 1336680 A JP1336680 A JP 1336680A JP S56110130 A JPS56110130 A JP S56110130A
Authority
JP
Japan
Prior art keywords
circuit
request
priority sequence
rom
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1336680A
Other languages
Japanese (ja)
Inventor
Koichi Shimomukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1336680A priority Critical patent/JPS56110130A/en
Publication of JPS56110130A publication Critical patent/JPS56110130A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To change the priority sequence by combination of the request sources without using a special circuit, by making the priority sequence have the degrees of freedom by use of the ROM. CONSTITUTION:The request receiving circuit 1 executes the request receiving operation, which is set by a timing signal T1 to the input H when a request signal is in the inputs RQ0-RQ7, and is reset when there is no request signal. When a request has been received by the circuit 1, the priority circuit 2 decides the address of its ROM, and decides the priority sequence of the request source by setting 1 bit of the data output. The permission holding circuit 3 executes the permission holding operation, which is set by a set time T2 to the input I by inputting the priority sequence decided by the circuit 2, and is reset when there is no request signal. The control circuit 4 generates the timing signals T1, T2 by monitoring the request signals REQ0-REQ7 and the permission signals ACK0-ACK7. In this way, it is possible to make the priority sequence have the degrees of freedom by changing the contents of the ROM of the circuit 2.
JP1336680A 1980-02-06 1980-02-06 Priority concurrent circuit Pending JPS56110130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1336680A JPS56110130A (en) 1980-02-06 1980-02-06 Priority concurrent circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1336680A JPS56110130A (en) 1980-02-06 1980-02-06 Priority concurrent circuit

Publications (1)

Publication Number Publication Date
JPS56110130A true JPS56110130A (en) 1981-09-01

Family

ID=11831092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1336680A Pending JPS56110130A (en) 1980-02-06 1980-02-06 Priority concurrent circuit

Country Status (1)

Country Link
JP (1) JPS56110130A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61109165A (en) * 1984-10-30 1986-05-27 レイセオン　カンパニ− Bus arbiter
JPS6478329A (en) * 1987-09-19 1989-03-23 Fujitsu Ltd Interruption controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61109165A (en) * 1984-10-30 1986-05-27 レイセオン　カンパニ− Bus arbiter
JPS6478329A (en) * 1987-09-19 1989-03-23 Fujitsu Ltd Interruption controller

Similar Documents

Publication Publication Date Title
JPS56110130A (en) Priority concurrent circuit
JPS5380132A (en) Signal control circuit
JPS5694596A (en) Memory control system
JPS54146552A (en) Interruption control system
JPS5332636A (en) Ic memory
JPS5431203A (en) Data communication control system
JPS57108912A (en) Bus driving circuit
JPS5710566A (en) Decoding circuit
JPS5671106A (en) Sequence control device
JPS57157621A (en) Digital error generating circuit
JPS57116458A (en) Information transmitter
JPS5542024A (en) Input circuit of electronic clock
JPS5761328A (en) Detection circuit of coincidence of changing point of two kinds of clock signal
JPS5597764A (en) Decoding circuit for dmi code
JPS5744329A (en) Control signal generating circuit
JPS57166728A (en) Discriminating circuit for pulse repetition period
JPS57130149A (en) System for interruption processing of microprogram control device
JPS5352320A (en) Output control circuit
JPS54121630A (en) Inter-unit interface system
JPS5624592A (en) Time setting system
JPS6416013A (en) Clock distribution circuit
JPS5765047A (en) Split phase type data generating system
JPS6413808A (en) Latching circuit
JPS5679535A (en) Counter control system
JPS54125078A (en) Timer