JPS5679535A - Counter control system - Google Patents

Counter control system

Info

Publication number
JPS5679535A
JPS5679535A JP15600779A JP15600779A JPS5679535A JP S5679535 A JPS5679535 A JP S5679535A JP 15600779 A JP15600779 A JP 15600779A JP 15600779 A JP15600779 A JP 15600779A JP S5679535 A JPS5679535 A JP S5679535A
Authority
JP
Japan
Prior art keywords
pulse
fed
state
counter
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15600779A
Other languages
Japanese (ja)
Inventor
Toshiro Kato
Hiroyasu Sumiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15600779A priority Critical patent/JPS5679535A/en
Publication of JPS5679535A publication Critical patent/JPS5679535A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K21/00Details of pulse counters or frequency dividers
    • H03K21/38Starting, stopping or resetting the counter

Landscapes

  • Selective Calling Equipment (AREA)

Abstract

PURPOSE:To enable to control the set state and reset state even with a counter without set and reset terminals, by enabling the clock terminal to transmit selectively the operation as a counter and initial state set. CONSTITUTION:To set the output of D flip-flops Fn-1, Fn, Fn+1... to ''1'', a pulse D1 is fed to an input line 6 and a pulse C1 is fed to an input line 7. The pulses D1, C1 have fine width which does not given any effect on the data, and the relation between D1 and C1 is socontrolled that the pulse C1 is fed while the pulse D is present. Thus when the pulses D1, C1 are fed, the output terminal Q outputs ''1'' independently of the state of D fli-flop. Then, each D flip-flop can be set to the initial state when the outputs are all at ''1''.
JP15600779A 1979-11-30 1979-11-30 Counter control system Pending JPS5679535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15600779A JPS5679535A (en) 1979-11-30 1979-11-30 Counter control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15600779A JPS5679535A (en) 1979-11-30 1979-11-30 Counter control system

Publications (1)

Publication Number Publication Date
JPS5679535A true JPS5679535A (en) 1981-06-30

Family

ID=15618282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15600779A Pending JPS5679535A (en) 1979-11-30 1979-11-30 Counter control system

Country Status (1)

Country Link
JP (1) JPS5679535A (en)

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