JPS5754431A - Test system - Google Patents

Abstract

PURPOSE:To perform easily functions which are difficult for test normally, by changing the polarity of clock for normal and test modes. CONSTITUTION:Since signals (a), (b), (c) are respectively 0, 1, 1, at a normal operating state, an inverting clock signal (f) of a clock signal (d) is outputted as a clock signal (g) with an AND gate 3 to be a count-up input to the counter 4. The carry output signal (h) of a counter 6 is 0 when the content of the counters 4-6 is all 1 and the signal (d) is 1, but the pulse width is the same as that of the signal (d). Next, at the test mode, since the signal (c), (d) are 0, a signal (f) is always 1. Since the signal (a) is 1, the inverting clock signal (e) of the signal (b) is outputted at a gate 3 to be a signal (g). The signal (h) is 0 when all the contents of the counters 4-6 are 1. Since this signal (h) produces the signal (g) with comparatively longer duty up to the next signal (g), it can be detected easily.