JPS55112039A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS55112039A
JPS55112039A JP2041579A JP2041579A JPS55112039A JP S55112039 A JPS55112039 A JP S55112039A JP 2041579 A JP2041579 A JP 2041579A JP 2041579 A JP2041579 A JP 2041579A JP S55112039 A JPS55112039 A JP S55112039A
Authority
JP
Japan
Prior art keywords
turned
low level
power consumption
features
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2041579A
Other languages
Japanese (ja)
Other versions
JPS6217897B2 (en
Inventor
Takeshi Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2041579A priority Critical patent/JPS55112039A/en
Publication of JPS55112039A publication Critical patent/JPS55112039A/en
Publication of JPS6217897B2 publication Critical patent/JPS6217897B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H03K19/09445—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors with active depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE:To reduce the power consumption by using the current limiting IGFET and then decide the charging time with gm of the enhancement-type IGFET, thus realizing a high-speed operation. CONSTITUTION:When input signal A1 is at a low level, both driving IGFETSM1 and M5 are turned off. At the same time, output D1 is charged by current limiting depletion-type IGFETM4 to be set to a high level along with the power consumption turned to zero each. In case signal A1 is at a high level with signal A2 at a low level each, IGFETSM1 and M3 are turned on with IGFETM2 turned off. And the potential of output D1 features a low level, and the power consumption at that moment is decided by gm of FETM3. Then in case signals A1 and A2 are at a low and high levels each, FETM1 is turned off with IGFETSM2-M5 turned on respectively. Thus the current can be controlled according to the scale of gm of FETM4, and output D1 features a low level. Furthermore, in case signals A1 and A2 are at the high levels, FETM1 plus M3-M5 are turned on with FETM2 turned off each. And D1 features a low level, and the current at that moment is decided by gm of FETM3.
JP2041579A 1979-02-22 1979-02-22 Logic circuit Granted JPS55112039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2041579A JPS55112039A (en) 1979-02-22 1979-02-22 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2041579A JPS55112039A (en) 1979-02-22 1979-02-22 Logic circuit

Publications (2)

Publication Number Publication Date
JPS55112039A true JPS55112039A (en) 1980-08-29
JPS6217897B2 JPS6217897B2 (en) 1987-04-20

Family

ID=12026398

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2041579A Granted JPS55112039A (en) 1979-02-22 1979-02-22 Logic circuit

Country Status (1)

Country Link
JP (1) JPS55112039A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5765927A (en) * 1980-10-13 1982-04-21 Hitachi Ltd Logical operation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5765927A (en) * 1980-10-13 1982-04-21 Hitachi Ltd Logical operation circuit

Also Published As

Publication number Publication date
JPS6217897B2 (en) 1987-04-20

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