JPS5617515A - Flip-flop circuit - Google Patents

Flip-flop circuit

Info

Publication number
JPS5617515A
JPS5617515A JP9339179A JP9339179A JPS5617515A JP S5617515 A JPS5617515 A JP S5617515A JP 9339179 A JP9339179 A JP 9339179A JP 9339179 A JP9339179 A JP 9339179A JP S5617515 A JPS5617515 A JP S5617515A
Authority
JP
Japan
Prior art keywords
transistor
potential
terminal
circuit
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9339179A
Other languages
Japanese (ja)
Other versions
JPS6316047B2 (en
Inventor
Takahisa Nishimura
Yoji Azuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9339179A priority Critical patent/JPS5617515A/en
Publication of JPS5617515A publication Critical patent/JPS5617515A/en
Publication of JPS6316047B2 publication Critical patent/JPS6316047B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
    • H03K3/2885—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit the input circuit having a differential configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To reduce the amount of power consumption by connecting the transistor having the differential working to the common emitter of the differential transistor in the FF circuit as well as to the collector of the highest-step transistor. CONSTITUTION:When the potential of reset input terminal In3 is lower than constant voltage source Vref4, the potential of output terminal 5 is affected by data input terminal In1 and clock input terminal In2. And the FF circuit has working. In case the potential of terminal In3 becomes higher than Vref4, transistor 25 is turned off with transistor 24 turned on each. Thus a low potential is obtained at terminal 5 to secure the reset state. In such constitution, the circuit does not need a number of current sources, thus reducing the amount of power consumption.
JP9339179A 1979-07-23 1979-07-23 Flip-flop circuit Granted JPS5617515A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9339179A JPS5617515A (en) 1979-07-23 1979-07-23 Flip-flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9339179A JPS5617515A (en) 1979-07-23 1979-07-23 Flip-flop circuit

Publications (2)

Publication Number Publication Date
JPS5617515A true JPS5617515A (en) 1981-02-19
JPS6316047B2 JPS6316047B2 (en) 1988-04-07

Family

ID=14081003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9339179A Granted JPS5617515A (en) 1979-07-23 1979-07-23 Flip-flop circuit

Country Status (1)

Country Link
JP (1) JPS5617515A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5813897A (en) * 1981-07-17 1983-01-26 株式会社奥村組 Drilling of horizontal hole under track
JPS59101924A (en) * 1982-11-30 1984-06-12 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン Set/reset latch circuit
JPS62501322A (en) * 1984-11-07 1987-05-21 プレツシ−　オ−バ−シ−ズ　リミテツド logic circuit
JPS62220016A (en) * 1986-03-20 1987-09-28 Fujitsu Ltd Clock both phases drive ff circuit with set or reset

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5813897A (en) * 1981-07-17 1983-01-26 株式会社奥村組 Drilling of horizontal hole under track
JPH0128200B2 (en) * 1981-07-17 1989-06-01 Okumura Corp
JPS59101924A (en) * 1982-11-30 1984-06-12 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン Set/reset latch circuit
EP0111055A2 (en) * 1982-11-30 1984-06-20 International Business Machines Corporation Latch circuit with differential cascode current switch logic
JPH025049B2 (en) * 1982-11-30 1990-01-31 Intaanashonaru Bijinesu Mashiinzu Corp
JPS62501322A (en) * 1984-11-07 1987-05-21 プレツシ−　オ−バ−シ−ズ　リミテツド logic circuit
JPS62220016A (en) * 1986-03-20 1987-09-28 Fujitsu Ltd Clock both phases drive ff circuit with set or reset
JPH0371814B2 (en) * 1986-03-20 1991-11-14 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS6316047B2 (en) 1988-04-07

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