JPH0371814B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention provides a clock dual-phase drive flip-flop circuit with a data set or reset function using a simple circuit configuration.

[Industrial application field]

The present invention is a clock double-phase drive FF (flip-flop) used in ultra-high-speed ICs such as optical communications.
Regarding the circuit, in detail, there is an actuating pair section that has a pair of transistors that open and close based on input signals of both positive and negative phases, and a new circuit that receives each output signal of both positive and reverse phases of the actuating pair section. and another operating pair section having a pair of other transistors that send out output signals of both positive and negative phases, and each operating pair section has an opening/closing operation based on each clock signal of both forward and reverse phases. The present invention relates to a clock dual-phase drive FF circuit with a set or reset function and a clock transistor.

[Conventional technology]

Note that in this specification, "the transistor is in an open state" means that the transistor is in a conductive state, and "the transistor is in a closed state" is used to mean that the transistor is in a cut-off state.

Conventionally, there has been a clock single-phase drive FF circuit with a set or reset function as shown in FIG.

The master side circuit 50 includes an operating pair section 5 having a pair of transistors 56 and 57 that open and close upon receiving input signals D of positive and negative phases at their bases.
1. Further, there is provided another actuation pair section 52 having a pair of other transistors 58 and 59 which receive the output signal of the actuation pair section 51 and send out output signals of both positive and negative phases.

Each of the operating pairs 51 and 52 includes a reference level transistor 53 and a clock transistor 54, each of which opens and closes in response to a DC current serving as a reference level, a clock signal C, and a reset signal R at their respective bases. Here, the reference level has a value intermediate between the H level and L level of the clock signal.

Furthermore, the transistor 58 of the other actuating pair section 52
A transistor 60 which opens and closes in response to a reset signal R as a base is connected in parallel.
Note that 61 is a constant current power supply.

On the other hand, the slave side circuit 70 includes an actuation pair section 52.
a slave operating pair section 71 having a pair of transistors 76 and 77 that open and close in response to output signals of both positive and negative phases;
1, and a pair of transistors 78 and 77 for outputting positive and negative phase output signals Q, respectively.

This circuit operates as follows.

As shown in the time chart of FIG. 4, when the input signal D is at L level and the reset signal R is at L level, transistor 56 is closed and transistor 57 is open. that time,
If the clock signal is at L level, it is at L level at point G, so the clock transistor 54 is closed and the reference level transistor 53 is opened, so that point E is at H level and point F is at L level.

Next, when clock signal C reverses to H level,
Since the clock transistor 54 and the clock transistor 73 of the slave side circuit 70 are in the open state, the I point becomes the L level and the J point becomes the H level, as in the case described above, and the positive phase output signal Q becomes the L level. becomes.

Next, consider the case where an H level signal is added as the reset signal R. However, the reset signal R
The H level voltage of the clock signal C may be higher than the midpoint between the H and L levels of the clock signal C, and the L level of the reset signal R may be equal to or approximately the same voltage as the L level of the clock signal C. This is because in transistors 53 and 54, the voltage at the base of transistor 53 is C, which is between the H level and L level of the base of transistor 54, so if the R signal is higher than the midpoint between the C signal and is open, transistor 53
This is because it is in a closed state.

In addition, the H level of transistors 58 and 59 is the base-emitter potential of transistors 85 and 86.
V _BE (usually 0.8V for NPN type) and current I _O of current source 87
and the value R of the resistor 88 (transistor 58,
59 H level)=RI _O +V _BE . In other words, by appropriately selecting the value of R, the transistors 58, 5
The base H level of 9 is determined. Therefore, in transistors 58, 59, 60, transistor 5
If the value of the resistor R is determined so that the H level of the transistors 8 and 59 is lower than the H level of the R signal, by setting the R signal to the H level, the transistors 58 and 5
9 is in a closed state, and transistor 60 is in an open state. A resistor R is provided for this purpose. Then, the reset signal R causes the transistor 60 to open while keeping the transistor 58 closed.

At this time, since the H level reset signal R is also applied to the base of the clock transistor 54, the clock transistor 54 also becomes open. Therefore, point E is maintained at H level, point F is maintained at L level, and the positive phase output signal Q is fixed at L level.

[Problems to be Solved by the Invention] By the way, in the conventional clock single-phase drive FF circuit using a single-phase clock signal and a reference level DC current, when the operating speed is increased,
Due to the shift in the rise and fall of the pulse due to the presence of a time constant, the waveform deformation of the clock signal pulse becomes large, making it impossible to switch between the two operating pairs 51 and 52 in a well-balanced manner, making it difficult to perform high-speed operation. It had some problems.

On the other hand, when providing a set or reset function to a clock dual-phase drive FF circuit suitable for high-speed operation, it is necessary to set only the positive or negative phase clock signal, as in the case of a clock single-phase drive FF circuit. Alternatively, fixing with a reset signal is not enough, and it is necessary to fix both positive and negative phase clock signals, resulting in a problem that the circuit configuration becomes complicated.

Therefore, the present invention has been made to solve the above problems, and has a simple circuit configuration.
Clock dual-phase drive FF for setting or resetting
It was created for the purpose of providing a circuit.

[Means for solving problems]

The present invention comprises, for example, as shown in FIG. 1, an operating pair section 1 having a pair of transistors 6 and 7 that open and close upon receiving input signals of both positive and negative phases at their respective bases;
and another operating pair section 2 having a pair of other transistors 8 and 9 that receive the output signals of both positive and reverse phases of the operating pair section 1 and send out new output signals of both positive and reverse phases. In a clock dual-phase drive FF circuit, each of the operating pairs 1 and 2 is equipped with clock transistors 3 and 4 that open and close in response to clock signals of both forward and reverse phases. A voltage conversion circuit 5 for converting the voltage into a voltage is provided, and a first transistor 10 that opens and closes in response to a set or reset signal as a base is connected in parallel to any one of the transistors 6, 7, 8, and 9. , the clock transistors 3 and 4 each have a second transistor which opens and closes in response to a set or reset signal as a base.
The transistors 11 and 12 are connected in parallel, while the first transistor 10 and the second transistor on the side of the active pair to which the first transistor 10 is connected are connected in parallel.
The predetermined level of the set or reset signal applied to the base of the transistor causes at least one of the emitter and collector to become open while leaving the other commonly connected transistor closed, and the level is reversed. In this case, the voltage is converted by the voltage conversion circuit so that the transistors other than the second transistor are returned to normal operation and the transistors themselves are closed.

[Effect]

For example, consider a case where an NPN type transistor is used and a first set transistor 10 is connected in parallel to the transistor 8.
When set or reset signals S and R are input,
The voltage conversion circuit 5 adjusts the voltage level of the set or reset signals S, R applied to the first transistor 10 and the second transistors 11, 12. That is, the H level voltage of the set or reset signals S and R applied to the first transistor 10 is higher than the H level voltage applied to the base of transistor 8, and the L level voltage is set higher than the H level voltage applied to the base of transistor 8. lower than the L level voltage. As a result, when an H level is input as the set or reset signal S, R, the first transistor 10 is opened while keeping the transistor 8 closed, and when an L level is input, the first transistor 10 is opened. becomes closed and transistor 8 returns to normal operation.
This is because electrons are attracted toward higher voltages.

Further, the H level voltage of the set or reset signals S, R applied to the second transistor 12 is equal to the H level voltage of the clock signal C, whose emitters are commonly connected to the corresponding transistors 11, 12.
The L level voltage of the set or reset signals S, R applied to the base of the clock signal C is lower than the L level voltage of the clock signal C. For ease of explanation, it is assumed that the second transistors 11 and 12 are stably in the switching region (saturation region and cutoff region), and the H level of one second transistor 11 and the other second transistor 12 is shall match.

As a result, the second transistor 11,
The H level of the set or reset signal input to the base of the second transistor 1 is applied to the second transistor 1 while keeping the clock transistors 3 and 4 closed.
When the clock transistors 1 and 12 are opened and the set or reset signal input to the bases of the second transistors 11 and 12 is at L level, the clock transistors 3 and 4 return to normal operation, and the second transistors 11 and 12 is in a closed state. Therefore, the point A is at the L level and the point B is at the H level, so that the positive phase output signal O is at the H level, and the negative phase output signal is at the L level.

〔Example〕

FIG. 2 shows an embodiment according to the present invention.

This embodiment is a master-slave type clock dual-phase drive FF circuit composed of NPN type transistors.

Reference numeral 20 denotes a master-side FF circuit, which includes an operating pair section 21 having a pair of transistors 26 and 27 that open and close in response to input signals D of both positive and negative phases at their bases. For example, input signal D,
The H level is -0.8V and the L level is -1.2V.
Further, there is provided another actuation pair section 22 having another pair of transistors 28 and 29 which receives the output signal of the actuation pair section 21 and sends out new output signals of both positive and negative phases.

Each of the operating pairs 21 and 22 is provided with clock transistors 23 and 24 which open and close in response to a reverse phase clock signal and a clock signal C, respectively. Here, it is assumed that the H level of the clock signals of the positive and negative phases at the K point and the M point is -2.4V, and the L level is -2.8V.

Further, a first transistor 30 which opens and closes in response to set or reset signals S and R as a base is connected to the transistor 28 of the actuating pair section 22, and the clock transistors 23 and 24 also receive the set or reset signal S. , R are connected in parallel.

A voltage conversion circuit 25 converts the set or reset signals S and R into predetermined voltages and applies them to the first and second transistors 30, 31, and 32. For example, assume that the H level at point U of the set or reset signal applied to the base of the first transistor 30 is -0.8V, and the L level is -1.7V.
This voltage is higher at the H level and lower at the L level than the H level -1.2V and the L level -1.6V at the Z and W points applied to the bases of the transistors 28 and 29, respectively. Furthermore, the set or reset signals S and R applied to the base of the second transistor 31 have an H level of - at point P.
2.0V, the L level is -2.9V, and the set or reset signals S and R applied to the base of the second transistor 32 have an H level of -2.9V at point T.
2.4V, L level is -3.3V. That is, the H level voltage -2.0V applied to the base of the second transistor 32 is applied to the positive and negative phase clock signals C,
H level voltage of C - 2.4V and H level voltage applied to the other second transistor 31 -
higher than 2.4V, the second transistor 31,3
The voltage conversion circuit 25 is configured such that the L level voltages -2.9V and -3.3V of the clock transistors C and C are lower than the L level voltage of -2.8V of the positive and negative phase clock transistors C.
It has been converted by

Reference numeral 40 denotes a slave side FF circuit, which includes a slave operation pair section 41 and another slave operation pair section 42 . The slave operation pair section 41 is the master side circuit 2
It has a pair of transistors 46 and 47 that open and close upon receiving positive and negative phase output signals from 0 to the base and send out positive and negative phase output signals. The other slave operation pair section 42 includes a pair of transistors 4 that open and close in response to the output signal from the slave operation pair section 41.
It has 8,49. Each slave operating pair part 41, 4
2 are provided with clock signals 83 and 84, respectively, which open and close in response to a clock signal C of positive and negative phases. In this example, a 1 mA constant current power supply is used.

Set or reset in this embodiment operates as follows. H as set or reset signals S and R
Enter the level. Then, the voltage conversion circuit 25
Accordingly, the voltage level of the set or reset signal applied to the bases of the first transistor 30 and the second transistors 31, 32 is adjusted.

The H level voltage of the set or reset signal applied to the first transistor 30 is higher than the voltage applied to the base of the transistor 28, whereas the L level voltage is lower. Therefore, when an H level is input as a set or reset signal, the first transistor 30 becomes open while keeping the transistor 28 closed, and when an L level is input, the first transistor 30 for setting etc. is in an open state. Closed, transistor 28 returns to normal operation.

Further, since the H level voltage of the set or reset signal applied to the base of the second transistor 32 is higher than the H level voltage at points M and K of the clock signal C of both positive and negative phases, the set or reset signal is applied to the base of the second transistor 32. Alternatively, when the H level of the reset signals S and R is input, the second transistors 31 and 32 are opened, and the clock transistors 23 and 24 remain closed.

Note that the H level voltage of the set or reset signals S, R applied to the base of the second transistor 31 is set lower than the voltage applied to the base of the second transistor 32;
When R is at H level, clock transistor 2
The second transistors 31 and 32 are in the open state without being pulled into the states 3 and 24.
This is because when the clock transistors 23 and 24 are driven to reciprocate between the two switching regions through the active region (unsaturated region), if the driving is fast, the time spent in the switching region increases. becomes short and cannot stay stably in the switching region. This is because the above voltage level, which is different from the voltage level determined by theory that assumes the switching region stays stably, works better in practice. be.

On the other hand, the L level of the set or reset signals S and R applied to the bases of the second transistors 31 and 32
The level voltage is a clock signal C of both positive and negative phases,
Since the voltage is lower than the L level voltage at the M point and the K point, when the L level of the set or reset signals S and R is input, the second transistors 31 and 32 are closed, and the clock transistors 23 and 24 are closed.
returns to normal operation. The above operation is made possible by making the amplitudes of the set or reset signals S, R larger than the amplitudes of the clock signal C, which has both positive and negative phases.

In this way, when H level is input as the set or reset signals S and R, point X becomes L level and point Y becomes H level. Furthermore, this signal is input to the FF circuit 40 on the slave side, and the positive phase output signal Q
An H level is output as a signal, and an L level is output as a reverse phase output signal.

In this embodiment, an NPN type transistor is used, but a PNP type transistor may be used, or both may be used in combination. When using PNP type,
It can be read as H→L, L→H, high→low, and low→high.

〔Effect of the invention〕

Since the present invention has the above-described configuration, it is possible to provide a set or reset function with a simple circuit configuration to a clock dual-phase drive FF circuit suitable for high-speed operation, resulting in excellent economy and workability. A clock dual-phase drive FF circuit with set or reset can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram explaining the principle of the present invention, FIG. 2 is a circuit diagram of an embodiment, FIG. 3 is a circuit diagram of a conventional example, and FIG. 4 is a time chart of the conventional example. DESCRIPTION OF SYMBOLS 1, 21... Working pair part, 2, 22... Other working pair part, 3, 4, 23, 24... Clock transistor, 10, 30... First transistor, 1
1, 12, 31, 32...second transistor,
5, 25... Voltage conversion circuit.

Claims (1)

[Claims] 1. A differential pair section 1 having a pair of transistors 6 and 7 that open and close by receiving input signals of both positive and negative phases at each base; Another differential pair section 2 having a pair of other transistors 8 and 9 receives each output signal and sends out new output signals of both positive and negative phases, and a clock signal of both positive and negative phases is used as a base. clock transistors 3 and 4 which open and close in response to the clock signal and control the output signals of the respective differential pair sections 1 and 2 using clock signals; and transistors 6, 7, 8, which constitute the differential pair sections 1 and 2. 9, and second transistors 11, 12 connected in parallel to each of the clock transistors 3, 4.
The first transistor 10 includes a differential pair section 1,
The high voltage level for the first transistor 10 to open/close is set higher than the high voltage level for the transistors 6, 7, 8, and 9 constituting the first transistor 2 to open/close, and lower than the low voltage level thereof. level and a set or reset signal corresponding to its low voltage level, and said second transistor 11,
12, a high voltage level for opening and closing the second transistors 11 and 12, which is set higher than the high voltage level for opening and closing the clock transistors 3 and 4 and lower than the low voltage level thereof; 1. A clock dual-phase drive FF circuit with set or reset, comprising a voltage conversion circuit 5 for applying a set or reset signal corresponding to a low voltage level to each base.