JPS5481736A - Ternary input circuit - Google Patents

Ternary input circuit

Info

Publication number
JPS5481736A
JPS5481736A JP15025577A JP15025577A JPS5481736A JP S5481736 A JPS5481736 A JP S5481736A JP 15025577 A JP15025577 A JP 15025577A JP 15025577 A JP15025577 A JP 15025577A JP S5481736 A JPS5481736 A JP S5481736A
Authority
JP
Japan
Prior art keywords
input
states
terminals
resistors
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15025577A
Other languages
Japanese (ja)
Inventor
Norimasa Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15025577A priority Critical patent/JPS5481736A/en
Publication of JPS5481736A publication Critical patent/JPS5481736A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Abstract

PURPOSE:To reduce the number of input terminals and input delivery lines, by forming three states corresponding to the binary output to two output terminals, to the three types of input states at the input terminal, through the provision of one input terminal and two output terminals. CONSTITUTION:The voltage dividing circuit 1 is constituted by connecting the resistors R1, R2 and R3 in series connection, and the element side of the resistors R3 and R1 is respectively connected to ground and the power supply VDD, and the junctions A and B of the resistors R1 and R2 and R2 and R3 are given with input. Further, the inverter circuits 2 and 3 of which threshold values are VT1 and VT2. Then, when the input states to the input terminal A are taken as three states of the application of the ground voltage V1, open and ground, the equations (1) and (2) are obtained. Where VT is the representing value of VT1 and VT2, and both VT1 and VT2 satisfy the equations. Thus, the number of input terminals and input delivery lines can be reduced by forming three states according to the binary output to two output voltage terminals corresponding to three types of input voltage stages at the input terminal.
JP15025577A 1977-12-13 1977-12-13 Ternary input circuit Pending JPS5481736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15025577A JPS5481736A (en) 1977-12-13 1977-12-13 Ternary input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15025577A JPS5481736A (en) 1977-12-13 1977-12-13 Ternary input circuit

Publications (1)

Publication Number Publication Date
JPS5481736A true JPS5481736A (en) 1979-06-29

Family

ID=15492935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15025577A Pending JPS5481736A (en) 1977-12-13 1977-12-13 Ternary input circuit

Country Status (1)

Country Link
JP (1) JPS5481736A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0486010A2 (en) * 1990-11-14 1992-05-20 Nec Corporation Multi-level logic input circuit
EP0589221A1 (en) * 1992-09-24 1994-03-30 Siemens Aktiengesellschaft Semiconductor integrated circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0486010A2 (en) * 1990-11-14 1992-05-20 Nec Corporation Multi-level logic input circuit
EP0486010A3 (en) * 1990-11-14 1994-05-25 Nec Corp Multi-level logic input circuit
EP0589221A1 (en) * 1992-09-24 1994-03-30 Siemens Aktiengesellschaft Semiconductor integrated circuit device

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