JPS554130A - Schmitt circuit - Google Patents

Schmitt circuit

Info

Publication number
JPS554130A
JPS554130A JP7687078A JP7687078A JPS554130A JP S554130 A JPS554130 A JP S554130A JP 7687078 A JP7687078 A JP 7687078A JP 7687078 A JP7687078 A JP 7687078A JP S554130 A JPS554130 A JP S554130A
Authority
JP
Japan
Prior art keywords
inverter
input
input terminal
mos inverter
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7687078A
Other languages
Japanese (ja)
Inventor
Masaharu Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7687078A priority Critical patent/JPS554130A/en
Publication of JPS554130A publication Critical patent/JPS554130A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0377—Bistables with hysteresis, e.g. Schmitt trigger

Abstract

PURPOSE:To make it possible to obtain high impedance by interposing two capacitors between input and output terminals through a series connection, by connecting the connection point to the 1st MOS inverter input terminal and then by connecting its output side to the input side of the 2nd MOS inverter. CONSTITUTION:The output terminal of MOS inverter 3 is connected to the input terminal of MOS inverter 4, and between signal input terminal 1 and the output terminal of inverter 4, capacitors C1 and C2 are connected in series. Then, the connection point is connected to the input terminal of inverter 3. Therefore, a Schmitt circuit with less current consumption and high input impedance can be obtained by a simple constitution.
JP7687078A 1978-06-23 1978-06-23 Schmitt circuit Pending JPS554130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7687078A JPS554130A (en) 1978-06-23 1978-06-23 Schmitt circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7687078A JPS554130A (en) 1978-06-23 1978-06-23 Schmitt circuit

Publications (1)

Publication Number Publication Date
JPS554130A true JPS554130A (en) 1980-01-12

Family

ID=13617666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7687078A Pending JPS554130A (en) 1978-06-23 1978-06-23 Schmitt circuit

Country Status (1)

Country Link
JP (1) JPS554130A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59167123A (en) * 1982-12-13 1984-09-20 ウエスタン，デジタル，コ−ポレ−シヨン High speed digital sample identifying circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59167123A (en) * 1982-12-13 1984-09-20 ウエスタン，デジタル，コ−ポレ−シヨン High speed digital sample identifying circuit

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