JPS5558627A - Logical operation circuit - Google Patents

Logical operation circuit

Info

Publication number
JPS5558627A
JPS5558627A JP13130378A JP13130378A JPS5558627A JP S5558627 A JPS5558627 A JP S5558627A JP 13130378 A JP13130378 A JP 13130378A JP 13130378 A JP13130378 A JP 13130378A JP S5558627 A JPS5558627 A JP S5558627A
Authority
JP
Japan
Prior art keywords
circuit
ttl
ttl circuit
transistors
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13130378A
Other languages
Japanese (ja)
Other versions
JPS5915217B2 (en
Inventor
Toshitaka Fukushima
Koji Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13130378A priority Critical patent/JPS5915217B2/en
Publication of JPS5558627A publication Critical patent/JPS5558627A/en
Publication of JPS5915217B2 publication Critical patent/JPS5915217B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/04—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using gas-filled tubes

Abstract

PURPOSE:To enhance the integration degree of a circuit by cascading the first TTL circuit and the second TTL circuit and making collector load resistances of respective output transistors common. CONSTITUTION:Signal inversion A0 having a polarity opposite to input signals A0 is obtained form the output terminal of the first TTL circuit dependent upon transistors Q1-Q4. Similarly, the second TTL circuit dependent upon transistors Q1- Q4 uses output signal inversion A0 of the first TTL circuit as the input, and A0 can be taken out at the output of the second TTL circuit, Collectors of output transistors Q4 of the first and the second TTL circuits are connected to the power source through common resistance R4. If transistor Q4 of the first TTL circuit is turned on (off), transistor Q4 of the second TTL circuit is turned off (on), so that no excessive load may be applied to resistance R4. As a result, the number of parts of the circuit can be reduced.
JP13130378A 1978-10-25 1978-10-25 logic circuit Expired JPS5915217B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13130378A JPS5915217B2 (en) 1978-10-25 1978-10-25 logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13130378A JPS5915217B2 (en) 1978-10-25 1978-10-25 logic circuit

Publications (2)

Publication Number Publication Date
JPS5558627A true JPS5558627A (en) 1980-05-01
JPS5915217B2 JPS5915217B2 (en) 1984-04-07

Family

ID=15054797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13130378A Expired JPS5915217B2 (en) 1978-10-25 1978-10-25 logic circuit

Country Status (1)

Country Link
JP (1) JPS5915217B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5830235A (en) * 1981-08-18 1983-02-22 Fujitsu Ltd Gate array
JPH08251015A (en) * 1986-05-30 1996-09-27 Advanced Micro Devices Inc Observability buffer

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60181131U (en) * 1984-05-11 1985-12-02 朝日金属株式会社 Wire for communication cables - Fixed pole hardware

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5830235A (en) * 1981-08-18 1983-02-22 Fujitsu Ltd Gate array
JPH08251015A (en) * 1986-05-30 1996-09-27 Advanced Micro Devices Inc Observability buffer

Also Published As

Publication number Publication date
JPS5915217B2 (en) 1984-04-07

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