JPS55158726A - Phase delay circuit - Google Patents

Phase delay circuit

Info

Publication number
JPS55158726A
JPS55158726A JP6529979A JP6529979A JPS55158726A JP S55158726 A JPS55158726 A JP S55158726A JP 6529979 A JP6529979 A JP 6529979A JP 6529979 A JP6529979 A JP 6529979A JP S55158726 A JPS55158726 A JP S55158726A
Authority
JP
Japan
Prior art keywords
phase
frequency characteristics
given
source
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6529979A
Other languages
Japanese (ja)
Inventor
Hiroshi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6529979A priority Critical patent/JPS55158726A/en
Publication of JPS55158726A publication Critical patent/JPS55158726A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/16Networks for phase shifting
    • H03H11/18Two-port phase shifters providing a predetermined phase shift, e.g. "all-pass" filters

Landscapes

  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:To simplify the operation when the phase is matched to the frequency characteristics, by securing the independent control between the phase and the frequency characteristics of the phase delay circuit and with no effect given to each other. CONSTITUTION:The video signal supplied from input terminal 101 is applied to the base (or the gate) of transistor TR102, and the inverse output and the noninverse output are extracted out of the collector (or the drain) and the emitter (or the source) or TR102 each. Thus the phase delay is given to the video signal. Then variable resistor 105 is connected between output terminal 107 and the emitter (or the source) of TR102 of the circuit, and furthermore capacitor 108 functioning as the capacitive element is connected in parallel to resistor 103 which is connected between the emitter (or the source) and power source +V. Then capacitor 106 is connected to the collector (or the drain). And the control is given to resistor 105 by capacitor 108 to eliminate the phase shift when the control is given to the frequency characteristics. Thus the independent control is secured between the phase and the frequency characteristics.
JP6529979A 1979-05-26 1979-05-26 Phase delay circuit Pending JPS55158726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6529979A JPS55158726A (en) 1979-05-26 1979-05-26 Phase delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6529979A JPS55158726A (en) 1979-05-26 1979-05-26 Phase delay circuit

Publications (1)

Publication Number Publication Date
JPS55158726A true JPS55158726A (en) 1980-12-10

Family

ID=13282893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6529979A Pending JPS55158726A (en) 1979-05-26 1979-05-26 Phase delay circuit

Country Status (1)

Country Link
JP (1) JPS55158726A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56152418U (en) * 1980-04-15 1981-11-14

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56152418U (en) * 1980-04-15 1981-11-14

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