JPS54107664A - Programmable counter - Google Patents

Abstract

PURPOSE:To perform the count operation of high frequency input without malfunction, by inserting the delay circuit to the control circuit of frequency dividing circuit, in the programmable counter consisting of the frequency dividing circuit of n stages cascade connection. CONSTITUTION:The terminal 21 is at L with the timing t1 and the input of the delay circuit 73 is at H. This input state is at H which is appeared at the output 27 of the delay circuit 73 at the timing t2. 27 sets or resets the frequency dividing circuits 1 to 4. At timing t2, 27 is restored to L. Thus, the output 21 of the frequency dividing circuit 1 is not inverted at timing t3. Then, normal count operation is made from timing t4. When 21, 23 and 24 are at L, the operation mentioned above is repeated, and the output of decimal count is obtained at 17 or 27.