JPS5580951A - Digital receiver - Google Patents

Digital receiver

Info

Publication number
JPS5580951A
JPS5580951A JP15553178A JP15553178A JPS5580951A JP S5580951 A JPS5580951 A JP S5580951A JP 15553178 A JP15553178 A JP 15553178A JP 15553178 A JP15553178 A JP 15553178A JP S5580951 A JPS5580951 A JP S5580951A
Authority
JP
Japan
Prior art keywords
window function
arithmetic
time
fourier conversion
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15553178A
Other languages
Japanese (ja)
Other versions
JPS6145909B2 (en
Inventor
Akira Fukui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15553178A priority Critical patent/JPS5580951A/en
Publication of JPS5580951A publication Critical patent/JPS5580951A/en
Publication of JPS6145909B2 publication Critical patent/JPS6145909B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To shorten the conversion time by carrying out the discrete Fourier conversion to the multiplication between the window function and the input digital signal with elimination of the areas close to the beginning and end of the integration time of the window function because the window function is small at those areas. CONSTITUTION:Digital signal f(nT) is supplied to arithmetic circuits 11-1P which perform the discrete Fourier conversion from input terminal 11, and thus the multiplication is given to each window function W(nT) at these arithmetic circuits for the discrete Fourier conversion. When the space is referred to a DELTAomega for the frequency to be detected at the arithmetic circuit, integration time NT is selected so that the minimum frequency omega0 which gives the zero point of Fourier conversion W(omega) of function W(nT) may be equal to DELTAomega. And the arithmetic circuit is selected so that the signal of each frequency component may be detected for the multi-frequency type dial signal. And the operation time of these arithmetic circuits is controlled by the timing of control circuit 12 and with omission of the areas close to the beginning and end of time NT. The output of the arithmetic circuit is applied to output logic circuit 13.
JP15553178A 1978-12-15 1978-12-15 Digital receiver Granted JPS5580951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15553178A JPS5580951A (en) 1978-12-15 1978-12-15 Digital receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15553178A JPS5580951A (en) 1978-12-15 1978-12-15 Digital receiver

Publications (2)

Publication Number Publication Date
JPS5580951A true JPS5580951A (en) 1980-06-18
JPS6145909B2 JPS6145909B2 (en) 1986-10-11

Family

ID=15608098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15553178A Granted JPS5580951A (en) 1978-12-15 1978-12-15 Digital receiver

Country Status (1)

Country Link
JP (1) JPS5580951A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58139548A (en) * 1981-12-22 1983-08-18 ウエステイングハウス・ブレイク・アンド・シグナル・ホールデイングス・リミテツド Railway signal receiver
JPS60500885A (en) * 1983-01-31 1985-06-06 モトロ−ラ・インコ−ポレ−テッド decoder circuit
JPS62222735A (en) * 1986-03-20 1987-09-30 Fujitsu Ltd Data collecting system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58139548A (en) * 1981-12-22 1983-08-18 ウエステイングハウス・ブレイク・アンド・シグナル・ホールデイングス・リミテツド Railway signal receiver
JPH0531338B2 (en) * 1981-12-22 1993-05-12 Uesuchinguhausu Bureiku Ando Shigunaru Co Ltd
JPS60500885A (en) * 1983-01-31 1985-06-06 モトロ−ラ・インコ−ポレ−テッド decoder circuit
JPH0422379B2 (en) * 1983-01-31 1992-04-16 Motorola Inc
JPS62222735A (en) * 1986-03-20 1987-09-30 Fujitsu Ltd Data collecting system

Also Published As

Publication number Publication date
JPS6145909B2 (en) 1986-10-11

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