JPS5580951A - Digital receiver - Google Patents
Digital receiverInfo
- Publication number
- JPS5580951A JPS5580951A JP15553178A JP15553178A JPS5580951A JP S5580951 A JPS5580951 A JP S5580951A JP 15553178 A JP15553178 A JP 15553178A JP 15553178 A JP15553178 A JP 15553178A JP S5580951 A JPS5580951 A JP S5580951A
- Authority
- JP
- Japan
- Prior art keywords
- window function
- arithmetic
- time
- fourier conversion
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To shorten the conversion time by carrying out the discrete Fourier conversion to the multiplication between the window function and the input digital signal with elimination of the areas close to the beginning and end of the integration time of the window function because the window function is small at those areas. CONSTITUTION:Digital signal f(nT) is supplied to arithmetic circuits 11-1P which perform the discrete Fourier conversion from input terminal 11, and thus the multiplication is given to each window function W(nT) at these arithmetic circuits for the discrete Fourier conversion. When the space is referred to a DELTAomega for the frequency to be detected at the arithmetic circuit, integration time NT is selected so that the minimum frequency omega0 which gives the zero point of Fourier conversion W(omega) of function W(nT) may be equal to DELTAomega. And the arithmetic circuit is selected so that the signal of each frequency component may be detected for the multi-frequency type dial signal. And the operation time of these arithmetic circuits is controlled by the timing of control circuit 12 and with omission of the areas close to the beginning and end of time NT. The output of the arithmetic circuit is applied to output logic circuit 13.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15553178A JPS5580951A (en) | 1978-12-15 | 1978-12-15 | Digital receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15553178A JPS5580951A (en) | 1978-12-15 | 1978-12-15 | Digital receiver |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5580951A true JPS5580951A (en) | 1980-06-18 |
JPS6145909B2 JPS6145909B2 (en) | 1986-10-11 |
Family
ID=15608098
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15553178A Granted JPS5580951A (en) | 1978-12-15 | 1978-12-15 | Digital receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5580951A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58139548A (en) * | 1981-12-22 | 1983-08-18 | ウエステイングハウス・ブレイク・アンド・シグナル・ホールデイングス・リミテツド | Railway signal receiver |
JPS60500885A (en) * | 1983-01-31 | 1985-06-06 | モトロ−ラ・インコ−ポレ−テッド | decoder circuit |
JPS62222735A (en) * | 1986-03-20 | 1987-09-30 | Fujitsu Ltd | Data collecting system |
-
1978
- 1978-12-15 JP JP15553178A patent/JPS5580951A/en active Granted
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58139548A (en) * | 1981-12-22 | 1983-08-18 | ウエステイングハウス・ブレイク・アンド・シグナル・ホールデイングス・リミテツド | Railway signal receiver |
JPH0531338B2 (en) * | 1981-12-22 | 1993-05-12 | Uesuchinguhausu Bureiku Ando Shigunaru Co Ltd | |
JPS60500885A (en) * | 1983-01-31 | 1985-06-06 | モトロ−ラ・インコ−ポレ−テッド | decoder circuit |
JPH0422379B2 (en) * | 1983-01-31 | 1992-04-16 | Motorola Inc | |
JPS62222735A (en) * | 1986-03-20 | 1987-09-30 | Fujitsu Ltd | Data collecting system |
Also Published As
Publication number | Publication date |
---|---|
JPS6145909B2 (en) | 1986-10-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6419827A (en) | Synchronizing device | |
JPS5580951A (en) | Digital receiver | |
US2862185A (en) | Electronic fm/fm to analog or digital converter | |
JPS5787617A (en) | Phase shift circuit | |
JPS5753172A (en) | Multifrequency signal oscillating system | |
JPS54107664A (en) | Programmable counter | |
JPS5755628A (en) | Phase comparing circuit and frequency synthesizer using it | |
JPS55163908A (en) | Digital tone control circuit | |
JPS55134541A (en) | Phase synchronous oscillator | |
SU705653A1 (en) | Generator of pseudorandom pulse train | |
JPS5566131A (en) | Integrated circuit | |
JPS5485070A (en) | Operation adjustment circuit of on timer and off timer | |
JPS5373047A (en) | Generation circuit for timing signal | |
JPS56138328A (en) | Frequency multiplying circuit | |
FR2436397A2 (en) | Interference component suppression circuit - processes test signals in nonlinear circuit with automatically adjustable dead zone | |
JPS5651180A (en) | Video signal binary device | |
JPS5571315A (en) | Limit cycle reduction system of digital filter | |
JPS57194378A (en) | Test circuit of electronic clock | |
JPS54134678A (en) | Effective value measuring apparatus | |
JPS56149117A (en) | Electronic timer | |
JPS5675711A (en) | Detection circuit for difference between frequencies | |
JPS5453847A (en) | Filter unit | |
JPS5412208A (en) | Gain-stabilized transmitter | |
JPS5516523A (en) | Preset channel selector | |
JPS5750146A (en) | Signal selector |