JPS54151369A - Programmable counter - Google Patents
Programmable counterInfo
- Publication number
- JPS54151369A JPS54151369A JP6024078A JP6024078A JPS54151369A JP S54151369 A JPS54151369 A JP S54151369A JP 6024078 A JP6024078 A JP 6024078A JP 6024078 A JP6024078 A JP 6024078A JP S54151369 A JPS54151369 A JP S54151369A
- Authority
- JP
- Japan
- Prior art keywords
- counter
- decoder
- constitution
- prescaler
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
Abstract
PURPOSE:To speed up the processing time by omitting the adders and subtractors, through the constitution of the programmable counter controlling frequency dividing ratio depending on the digital signal externally with high speed variable prescaler and counter and decoder. CONSTITUTION:The high speed prescaler 3, first counter 4, second counter 5, first decoder 6, and second decoder 7 are connected between the signal input terminal 1 and the signal output terminal 2. With this constitution for the programmer, the prescaler 3 selects the frequency dividing ratio from U to L, and U(Ps+S) sets of pulses are inputted to the terminal 1. Next, when L{PM-(Ps+S)+M} sets of pulses are inputted to the terminal 1, N=(S+10M)+(Ps+10PM), frequency dividing ratio, is obtained with U=11 and L=10. That is, by setting numeral S+10M with decoders 6 and 7, desired frequency ratio N can be obtained by adding and subtracting the numeral Ps+10PM to this.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6024078A JPS6013576B2 (en) | 1978-05-19 | 1978-05-19 | programmable counter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6024078A JPS6013576B2 (en) | 1978-05-19 | 1978-05-19 | programmable counter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54151369A true JPS54151369A (en) | 1979-11-28 |
JPS6013576B2 JPS6013576B2 (en) | 1985-04-08 |
Family
ID=13136449
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6024078A Expired JPS6013576B2 (en) | 1978-05-19 | 1978-05-19 | programmable counter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6013576B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57129030A (en) * | 1981-02-04 | 1982-08-10 | Hitachi Ltd | Variable frequency divider |
JPS6316724U (en) * | 1986-07-18 | 1988-02-03 |
-
1978
- 1978-05-19 JP JP6024078A patent/JPS6013576B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57129030A (en) * | 1981-02-04 | 1982-08-10 | Hitachi Ltd | Variable frequency divider |
JPS6316724U (en) * | 1986-07-18 | 1988-02-03 |
Also Published As
Publication number | Publication date |
---|---|
JPS6013576B2 (en) | 1985-04-08 |
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